CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse

Abstract

Abstract. In synchronous circuit design, new levels of abstraction above RTL allow the designer to model, simulate, debug and explore various architectures more efficiently than before. These are known as transaction level modeling. The translation between signals at different levels of abstraction is performed by pieces of code called transactors, mainly for the purpose of simulation. This paper identifies a set of asynchronous abstractions suitable for asynchronous transaction level modeling. Based on these models, we show that asynchronous CSP-based transactors can bring many more benefits than their synchronous counterparts, while being simpler to describe. We show how they can be used to automatically generate complex SystemC templates and hardware-software links, and automatically build network-on-chip interfaces facilitating IP reuse in embedded systems. Tools were developed after the techniques described in this paper. They are used in a case study to describe an asynchronous IP from transaction levels to RTL, demonstrating the automatic generation of various complex parts of the design and the minimum amount of specifications required from the designer.

Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions

“…For example in [26], interface protocols are specified formally using PSL SEREs (extended regular expressions), and transactors are automatically generated from such a specification, using a SERE to finite state machine transformation. The authors of [27] notice that most ESL tools are designed to deal with synchronous interconnects. They discuss asynchronous transaction level modeling and show that CSP (Communicating Sequential Processes) based transactors can be used to perform CSP to TLM-PV and TLM-PV to CSP translations, and that RTL interfaces can also be generated.…”