Abstract. In synchronous circuit design, new levels of abstraction above RTL allow the designer to model, simulate, debug and explore various architectures more efficiently than before. These are known as transaction level modeling. The translation between signals at different levels of abstraction is performed by pieces of code called transactors, mainly for the purpose of simulation. This paper identifies a set of asynchronous abstractions suitable for asynchronous transaction level modeling. Based on these models, we show that asynchronous CSP-based transactors can bring many more benefits than their synchronous counterparts, while being simpler to describe. We show how they can be used to automatically generate complex SystemC templates and hardware-software links, and automatically build network-on-chip interfaces facilitating IP reuse in embedded systems. Tools were developed after the techniques described in this paper. They are used in a case study to describe an asynchronous IP from transaction levels to RTL, demonstrating the automatic generation of various complex parts of the design and the minimum amount of specifications required from the designer.

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Abstract. Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but for handling interfaces between CPUs and FPGAs. The usual difficulties are the discovery of interface libraries and tools, and the selection of methods to debug and optimize the communications. Our GALS (Globally Asynchronous Locally Synchronous) system design framework, which was originally designed for embedded systems, happens to be outstanding for programming and debugging HPC systems with reconfigurable FPGAs. Its co-simulation capabilities and the automatic regeneration of interfaces allow an incremental design strategy in which the HPC programmer co-designs both software and hardware on the host. It then provides the flexibility to move components from software abstraction to Verilog/VHDL simulator, and eventually to FPGA targets with automatic generation of asynchronous interfaces. The whole design including the generated interfaces is visible in a graphical view with real-time representation of simulation events for debugging purpose.

Abstract