Cu Clip-Bonding Method With Optimized Source Inductance for Current Balancing in Multichip SiC MOSFET Power Module

Wang, Laili; Zhang, Tongyu; Yang, Fengtao; Ma, Dingkun; Zhao, Cheng; Pei, Yunqing; Gan, Yongmei

doi:10.1109/tpel.2022.3141373

Cited by 35 publications

(3 citation statements)

References 27 publications

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“…This approach could potentially mitigate the current imbalance to a certain degree but it also increases the parasitic inductance, which can slow down the switching speed or pose switching oscillations. A method with a similar principle can be found in [85]. To control the parasitics on the connecting wires, copper clips are utilized to supplant bonding wires.…”

Section: A Passive Methodologiesmentioning

confidence: 99%

Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions

Zhao

Wang

et al. 2023

IEEE Trans. Power Electron.

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Power semiconductor devices are often connected in parallel to increase the current rating of the power conversion systems. However, due to mismatched circuit parameters or semiconductor fabrication discrepancies, the current of paralleled power semiconductor devices can be unbalanced, which potentially leads to accelerated aging and long-term reliability issues. The fast-switching speed of silicon carbide (SiC) devices aggravates this problem due to its higher sensitivity to parasitic parameters. Numerous efforts have been dedicated to analyzing and addressing the current imbalance issue of paralleling SiC devices. This article comprehensively summarizes and presents state-of-the-art research regarding the current imbalance in paralleled SiC devices. Degree of imbalance is proposed to comprehensively quantify the current mismatch. Starting with mechanism analysis, different types of current imbalance are categorized. Various device parameters and the package layout that impact the current distribution are investigated. The existing solutions including passive methods and active methods are concluded and categorized. This work also incorporates insight into the future development needs of high-power multichip SiC module packaging and driving technologies.

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Section: A Passive Methodologiesmentioning

confidence: 99%

Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions

Zhao

Wang

et al. 2023

IEEE Trans. Power Electron.

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“…To overcome the mutual inductance between different current paths, Yang et al [18] proposed a SiC MOSFET power module with an interleaved planar structure in which the currents of two adjacent die were in opposite directions. Another type of wire-bondless interconnection packaging is using a copper clip to replace the bonding wire [19], [20].…”

mentioning

confidence: 99%

“…Numerous studies have reported on novel SiC MOSFET packages and their initial electrical properties [14], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25]. However, the long-term reliability and robustness of packaging are key factors in applications [28], [29].…”

mentioning

confidence: 99%

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

Chen

Jiang

Meda

et al. 2023

IEEE Trans. Electron Devices

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SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wirebonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of 8 × 8 × 0.75 mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The

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An Optimization Design Method of Multi-chip Parallel Power Module Based on Machine Learning

Wang,

Huang,

et al. 2023

Lecture Notes in Electrical Engineering

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Cu Clip-Bonding Method With Optimized Source Inductance for Current Balancing in Multichip SiC MOSFET Power Module

Cited by 35 publications

References 27 publications

Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions

Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

An Optimization Design Method of Multi-chip Parallel Power Module Based on Machine Learning

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