Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrier

Abstract

A CdSi layered-gate-structured MOSFET with Ta and TaN stacked barrier layers fabricated using a Cu damascene process has been developed for high-performance and reliable Si ULSI devices. A sheet resistance of 0.5 ohm/sq. was achieved with a 0.25-pm gate length. The Ta and TaN layers guarantee reliable gate oxide (7.5 nm) after 500°C thermal processing in nitrogen with forming gas annealing.

Investigation of Cu/TaN Metal Gate for Metal-Oxide-Silicon Devices

“…Consequently, the gate electrode might be formed with stack structure that consists of a low resistivity metal and refractory metal nitride layers. 12,16,17 Wherever it is possible, the low resistivity layer serves as the major conduction material and metal nitride layer serves as the threshold voltage control material.…”

“…18 Investigating the feasibility of using Cu/TaN x at the front-end-of-line ͑FEOL͒, as the gate electrode, becomes natural. 16 The use of Cu/TaN x at both the FEOL and back-end-of-line ͑BEOL͒ can simplify the management of production line and reduce the cost-ofownership because the equipment for BEOL can share with FEOL. Therefore, Cu/TaN x gate is one of the desirable gate structures.…”