For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

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Abstract-Trapping is one of the most deleterious effects that limit performance and reliability in GaN HEMTs. In this paper, we present a methodology to study trapping characteristics in GaN HEMTs that is based on current-transient measurements. Its uniqueness is that it is amenable to integration with electrical stress experiments in long-term reliability studies. We present the details of the measurement and analysis procedures. With this method, we have investigated the trapping and detrapping dynamics of GaN HEMTs. In particular, we examined layer location, energy level, and trapping/detrapping time constants of dominant traps. We have identified several traps inside the AlGaN barrier layer or at the surface close to the gate edge and in the GaN buffer.

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