2020
DOI: 10.26577/phst.2020.v7.i2.06
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Current and capacitance hysteresis in porous semiconductor nanofilms

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Cited by 2 publications
(1 citation statement)
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“…applied 10, 20, and 30 min. as etching times in order to crystalline silicon n-type (111) and (100) wafers in order to electrochemically etch PS [35][36][37][38]. It was confirmed that, while utilizing the electrochemical etching technique, the PS's depth, width, and roughness increased as the etching time rose [39][40][41][42][43][44].…”
Section: Introductionmentioning
confidence: 83%
“…applied 10, 20, and 30 min. as etching times in order to crystalline silicon n-type (111) and (100) wafers in order to electrochemically etch PS [35][36][37][38]. It was confirmed that, while utilizing the electrochemical etching technique, the PS's depth, width, and roughness increased as the etching time rose [39][40][41][42][43][44].…”
Section: Introductionmentioning
confidence: 83%