Current-driven wire planning for electromigration avoidance in analog circuits

Lienig, Jens; Jerke, Goeran

doi:10.1109/aspdac.2003.1195125

Cited by 19 publications

(24 citation statements)

References 10 publications

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“…They use a quasi-3D model to hierarchically calculate current density and perform thermal simulations to check violations in wires and vias. Lienig et al [8] use post-route area adjustment of critical net structures to size wires and vias and thereby fix current density violations. Banerjee et al [1] study the extent of EM failure under AC bipolar stress and joule heating in signal nets.…”

Section: Introductionmentioning

confidence: 99%

On potential design impacts of electromigration awareness

Kahng

Nath

Rosing

2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Reliability issues significantly limit performance improvements from Moore's-Law scaling. At 45nm and below, electromigration (EM) is a serious reliability issue which affects global and local interconnects in a chip and limits performance scaling. Traditional IC implementation flows meet a 10-year lifetime requirement by overdesigning and sacrificing performance. At the same time, it is well-known among circuit designers that Black's Equation [2] suggests that lifetime can be traded for performance. In our work, we carefully study the impacts of EM-awareness on IC implementation outcomes, and show that circuit performance does not trade off so smoothly with mean time to failure (MTTF) as suggested by Black's Equation. We conduct two basic studies: EM lifetime versus performance with fixed resource budget, and EM lifetime versus resource with fixed performance. Using design examples implemented in two process nodes, we show that performance scaling achieved by reducing the EM lifetime requirement depends on the EM slack in the circuit, which in turn depends on factors such as timing constraints, length of critical paths and the mix of cell sizes. Depending on these factors, the performance gain can range from 10% to 80% when the lifetime requirement is reduced from 10 years to one year. We show that at a fixed performance requirement, power and area resources are affected by the timing slack and can either decrease by 3% or increase by 7.8% when the MTTF requirement is reduced. We also study how conventional EM fixes using per net Non-Default Rule (NDR) routing, downsizing of drivers, and fanout reduction affect performance at reduced lifetime requirements. Our study indicates, e.g., that NDR routing can increase performance by up to 5% but at the cost of 2% increase in area at a reduced 7-year lifetime requirement.

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Section: Introductionmentioning

confidence: 99%

On potential design impacts of electromigration awareness

Kahng

Nath

Rosing

2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…2 Under EM consideration, the wire width should vary according to its current density. Consider an instance created by [10]-a signal net with three current sources and four current sinks-as shown in Fig. 1(a).…”

Section: Introductionmentioning

confidence: 99%

“…Although we can refine it, a significant amount of layout change is inevitable. Considering EM during routing instead, prior works [10] and [11] propose heuristics and have the lower wire area 154 [see Fig. 1(d)] and 144 [see Fig.…”

Section: Introductionmentioning

confidence: 99%

WiT: Optimal Wiring Topology for Electromigration Avoidance

Jiang

Chang

2012

IEEE Trans. VLSI Syst.

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Abstract-Due to excessive current densities, electromigration (EM) may trigger a permanent open-or short-circuit failure in signal wires or power networks in analog or mixed-signal circuits. As the feature size keeps shrinking, this effect becomes a key reliability concern. Hence, in this paper, we focus on wiring topology generation for avoiding EM at the routing stage. Prior works tended towards heuristics; on the contrary, we first claim this problem belongs to class P instead of class NP-hard. Our breakthrough is, via the proof of the greedy-choice property, we successfully model this problem on a multi-source multi-sink flow network and then solve it by a strongly polynomial time algorithm. Experimental results prove the effectiveness and efficiency of our algorithm.

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“…After floorplanning, placement and routing, a verification of current densities is performed in order to identify regions with excessive currentdensity stress [3]. The terminal current values required for a currentdensity calculation are obtained from a prior simulation of analogand mixed-signal circuits or a current estimation within digital circuits [3,6,10]. Based on these provided current data, our methodology utilizes a newly introduced design stage -the current-densitydriven layout decompaction.…”

Section: Overviewmentioning

confidence: 99%

“…However, this most likely creates a high percentage of over-designed (i.e., route space wasting) net segments without any guarantee of current-density correctness. Secondly, the routing is performed with a current-flow-aware and hence current-density-driven wire planning and routing tool (e.g., [1,6]). Here, one of the problems is the determination of segmentspecific current data prior to routing.…”

Section: Introductionmentioning

confidence: 99%

Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs

Jerke

Lienig²,

Scheible

2004

Proceedings of the 41st Annual Design Automation Conference

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The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated circuits. We present a new approach that addresses this electromigration issue by considering current density and inhomogeneous current-flow within arbitrarily shaped metallization patterns during physical design. Our proposed methodology is based on a post-route modification of critical layout structures that utilizes current-density data from a previously performed current-density verification. It is especially tailored to overcome the lack of current-flow consideration within existing routing tools. We also present experimental results obtained after successfully integrating our methodology into a commercial IC design flow.

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Current-driven wire planning for electromigration avoidance in analog circuits

Cited by 19 publications

References 10 publications

On potential design impacts of electromigration awareness

On potential design impacts of electromigration awareness

WiT: Optimal Wiring Topology for Electromigration Avoidance

Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs

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