Current-mode analog integrated circuit for focal-plane image compression

Oliveira, Fernanda D. V. R.; Haas, Hugo L.; Gomes, Jonas; Petraglia, Antonio

doi:10.1109/sbcci.2012.6344438

Cited by 1 publication

(1 citation statement)

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“…The chips from both generations use the same lenses and structure shown in [11], but a new circuit board was designed to adapt for the requirements of the new chip. For example, the transistors from the first generation operate with a power supply of 3.3 V, while the second generation ones work with 1.8 V. Aiming at comparing the results from both chips, the same targets used for the first generation [18] were employed to test the new chip. Those are black and white images with geometrical shapes that allow for the visualization and first evaluation of the DPCM and VQ stages, as well as the final decoded image.…”

Section: Resultsmentioning

confidence: 99%

Focal-Plane Compression Imager with Increased Quantization Bit Rate and DPCM Error Modeling

Oliveira¹,

Lopes²,

Gomes³

et al. 2020

JICS

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Focal-plane processing is the target of many studies due to its potential for enhancing the speed of the vision system flow. With focal-plane processing it is possible to perform parallel processing throughout the entire matrix. In order to alleviate A/D conversion and transmission constraints, analog image compression is implemented at the focal plane, thereby reducing the amount of data to be transmitted and the bandwidth requirements. The ADC is performed at the focal plane as well, after the compression operation whose realization is based on differential pulse-code modulation (DPCM), linear transform and vector quantization (VQ) applied on every 4 × 4 pixel block using current-mode circuits. This paper presents experimental results obtained from a second-generation version of the image sensor. Among these results we can point out the presentation of different captured images and the modeling of errors that were identified during the experimental tests. Since the source of these errors is the DPCM stage, the modeling concerns the bits that refer to the mean block luminance results. The error modeling procedure was developed considering the relationship between the pixel integration period and the DPCM quantizer threshold values. The main contributions of the second-generation chip in comparison to the previous realization are: increase of the vector quantizer complexity, number of bits per pixel, pixel matrix size, and the use of cascode current mirrors in the linear transform matrix. The image sensor advanced in this paper was fabricated in a standard 180 nm CMOS process.

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Section: Resultsmentioning

confidence: 99%