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Active pixel sensors are very suitable for the implementation of a large variety of image processing algorithms at the focal plane level. We propose a new focal plane image compression algorithm that is implemented with 607 transistors inside every 4 × 4 pixel block of a CMOS imager, using conventional 0.35 μm integration technology. We describe the theory of the proposed method, which is based on DPCM of the average block luminance and on VQ of four low-frequency components obtained by a linear transformation applied to the local pixels. We introduce the analog hardware of the pixel block and, to validate our design, present image coding results obtained from electrical Spice simulations of 64 pixel blocks.

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A new model for the sensitivity analysis of inner products to CMOS analog hardware implementation is proposed. It is derived from Spice simulations of the circuits to be implemented, and is required for the design of analog image compression systems based on vector quantization at the focal plane of CMOS imaging sensors. The model is shown to be equivalent to a simpler, previously introduced model, if the errors caused by the fabrication process are around 6%. For 1.5% errors, the results differ from the theoretical predictions made by the previous model. Image compression results and the layout of the fabricated circuit, currently under test, are presented.