A CMOS imaging system featuring focal-plane compression based on DPCM and VQ

Oliveira, Fernanda D. V. R.; Haas, Hugo L.; Gomes, Jonas; Petraglia, Antonio

doi:10.1109/lascas.2012.6180300

Cited by 4 publications

(2 citation statements)

References 11 publications

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“…Finally, a block-wise operation reshapes all 16 × 1 vectors into 4 × 4 blocks, and the blocks are organized into an 8 × 8 matrix with 64 blocks, so that the final resolution is 32 × 32. This circuit has been designed so that the comparator output bits [9], [10], denoted as o 01 (n), …, o 07 (n), are a quantized description of the absolute value the prediction error, i.e. |e(n)|.…”

Section: Dpcm Bitsmentioning

confidence: 99%

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CMOS Image Sensor Featuring Current-Mode Focal-Plane Image Compression

Oliveira¹,

Haas²,

Gomes³

et al. 2020

JICS

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The interest in focal-plane processing techniques, by which image processing is carried out at the pixel level, has increased since the advent of active pixel sensors in the middle 90’s. By sharing processing circuitry by a group of neighboring pixels such techniques enable high-speed imaging operation and massive parallel computation. Focal-plane image compression is particularly interesting, because it allows for further reduction in data rates. The proposed approach also benefits from processing currents rather than voltages, which not only suits current-mode APS imagers, but also enables the circuits to operate at low voltage supply levels and achieve high speed. Moreover, arithmetic computations such as additions and scaling are easily implemented in current mode. Whereas current-mode imaging architectures produce higher fixed pattern noise (FPN) figures than their voltage-mode counterparts, low FPN can be achieved by applying correlated double sampling (CDS) and gain correction techniques. This work presents a 32 × 32 gray-level imaging integrated circuit featuring focal plane image compression, such that for each 4 × 4 pixel block, analog circuits implement differential pulse-code modulation, linear transform, and vector quantization. Other processing functions implemented in the chip are CDS and A/D conversion. Theoretical details are described, as well as the test setup of the chip fabricated in a 0.35 μm CMOS process. To validate the proposed technique, experimental results and captured photographs are shown. The CMOS imager compresses captured images at 0.94 bits/pixel for an overall power consumption below 40 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/c mare preserved in the decoded images.

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Section: Dpcm Bitsmentioning

confidence: 99%

“…The pseudo-code necessary to generate the image is also shown in this section. Other experimental results from the chip can be found in [10], [11].…”

Section: Introductionmentioning

confidence: 99%