Current-mode clock distribution

Abstract

Abstract-We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flipflop (CMPFF) using a representative 45nm CMOS technology. When the CMPFF is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage mode clocks.

Differential current-mode clock distribution

“…The previous differential current-mode schemes, however, were one-to-one data connections whereas clock networks are, by definition, a one-to-many signal distribution. A oneto-many CM clocking scheme based on CM current-pulsed FF [5] offered a large CDN power savings compared to a VM scheme. However, it consumes high static power and is highly susceptible to noise.…”

“…The DCMPFF extends the previous single input current CM pulsed FF (CMPFF) [5] to have two complementary input currents, I(IN+) and I(IN-). These inputs can be either positive or negative depending on the current direction, however, the DCMPFF is only sensitive when I(IN+) has a push-current and I(IN-) has a pull-current to mimic an edgetriggered behavior.…”

“…The complementary pushpull currents also helps simplify the design of the current Tx which can generate the currents from a single input voltage. The CC compares two complementary currents which are combined using an inverter amplifier that enables smaller transistors in the CC (M2-M3) compared to the prior singleended CMPFF CC [5]. Due to the lower logical effort of M2-M3, the DCMPFF requires less input current and consumes less power.…”

“…An immediate solution is to use wide wires, but this results in higher energy per bit because of the large railto-rail voltage swing. An alternative signaling scheme such as CM, however, can eliminate transmission line repeaters in addition decreasing necessary voltage swing to significantly reduce power [5]- [8].…”

“…In this paper, we extend the de novo CM clocking concept [5] to implement and analyze the first DCM clock distribution and a new DCM pulsed D-type FF. The clock (CLK) input to the FF is a CM receiver and the data input (D) and output (Q) are VM.…”