Current State of the Mixed-Signal Test Bus 1149.4

Hannu, Jari; Häkkinen, Juha; Voutilainen, Juha-Veikko; Jantunen, Heli; Moilanen, M.

doi:10.1007/s10836-012-5339-7

Cited by 4 publications

(4 citation statements)

References 10 publications

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“…As trace 4 is not defective in all PCBs, voltage ratios in Fig. 14a look similar apart from some deviations in the defective PCBs due to the other traces.…”

Section: T Race 4 Testingmentioning

confidence: 71%

“…On the other hand, the AXI solution is expensive and slow for testing every manufactured PCB, especially for electronics where long-term reliability is not important. Moreover, boundary-scan testing which has seen great progress from standardization point of view is not always applicable, this is due to diversity of today PCBs which may contain non-boundary-scan-compliant components [4,11].…”

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confidence: 99%

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Application of Contactless Testing to PCBs with BGAs and Open Sockets

Renbi

Delsing

2015

J Electron Test

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“…As trace 4 is not defective in all PCBs, voltage ratios in Fig. 14a look similar apart from some deviations in the defective PCBs due to the other traces.…”

Section: T Race 4 Testingmentioning

confidence: 71%

mentioning

confidence: 99%

Application of Contactless Testing to PCBs with BGAs and Open Sockets

Renbi

Delsing

2015

J Electron Test

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“…However, up to now, IEEE 1149.4 has not been widely used commercially due to several reasons, such as its IC area concern; its implementation costs; its low measurement frequency bandwidth, which is approximately 1 MHz; and its higher measurement error, which may arise because of the higher impedance of silicon switches [8,22]. With this situation, boundary-scan defect coverage remains unimproved in the same manner as coverage with IEEE 1149.1.…”

Section: Boundary-scan and Current Limitationsmentioning

confidence: 99%

Contactless Testing of Circuit Interconnects

Renbi

Delsing

2015

J Electron Test

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State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 μm and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.

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“…An upgrade of the standard has been discussed in [Han12]. In two papers [San09,Lin14], the sinus output response was suggested for better characterisation, while the second paper introduces precision on-chip measurements.…”

Section: Irf Detection Using Boundary-scan Techniquesmentioning

confidence: 99%

Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems

Ebrahimi¹

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Current State of the Mixed-Signal Test Bus 1149.4

Cited by 4 publications

References 10 publications

Application of Contactless Testing to PCBs with BGAs and Open Sockets

Application of Contactless Testing to PCBs with BGAs and Open Sockets

Contactless Testing of Circuit Interconnects

Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems

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