Current status and future perspectives of wafer bonding (Smart Cut/spl trade/) SOI technology

Yoshimi, M.; Mazuré, C.

doi:10.1109/icsict.2004.1435000

Cited by 2 publications

(1 citation statement)

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“…With the inception of Unibond and smart cut technology [4,5], the possibility of manufacturing 300 mm SOI wafers became a reality [4]. Extensive research on ultra-thin body (UTB) SOI MOSFETs [5] has increased the development of SOI-based devices replacing classical MOSFETs.…”

Section: Silicon On Insulatormentioning

confidence: 99%

Evaluation of Device Fabrication from FET to CFET: A Review

Prasanna¹,

Kumar²,

Ch³

et al. 2021

J. Nano- Electron. Phys.

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Semiconductor industry is advancing day by day to meet the needs of society. As technology grows, the transistor density in an IC increases to augment the performance keeping down the size. Due to the miniaturization of transistors over the past decades, technological progress is in great demand. Vigorous scaling of a planar MOSFET has outaged its nanoscale era due to significant complications associated with increased parasitic capacitance, subthreshold leakage current, thinner gate oxides, which led the researchers to develop and innovate new devices with improved efficiency at low power parameters and reduced short channel effects (SCEs). In this review article, recent technological demand for FETs with multiple gates has been explored and reviewed with advancements. Devices with multiple gates show better performance than conventional FETs due to their steep subthreshold slope, lower leakage current and excellent electrostatic properties even in nanometer regime channel lengths. A triple gate FET and a gate all around FET further improve gate control over the channel. Using FinFET based multi-gate technology, gate control over the channel charge could be increased along with a reduction in parasitic capacitances. To explore the discontinuity of research, the challenges of FinFET technologies have also been addressed along with the introduction of emerging devices. Nanosheets and forksheets address these problems well, as gate structures are stacked on top of each other to form a multiple gate structure that supports enhanced gate control over the channel, whereas C-FET introduces 3D scaling by "folding" the nFET on top of the pFET by exploiting the full edge possibilities of device scaling in 3D.

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Section: Silicon On Insulatormentioning

confidence: 99%