Current status and future prospect of the Nb-based fabrication process for single flux quantum circuits

Abstract

The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a J c = 2.5 kA cm −2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a J c = 10 kA cm −2 , nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a J c = 40 kA cm −2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.

Evaluation of a Tunnel Barrier in Superconducting NbN Junctions With Subharmonic Gap Structures

“…Both regions would have transmitted the singleparticle current, but only the thinner region would have carried the subgap current due to its higher transparency. This transparency can be derived from (2). It is about 0.2 from theoretical prediction for [10]) and almost independent of the measured current density.…”

“…Using this simple method, we can derive the current density of an NbN tunnel junction with a thinner barrier by using (1) and (2). Equation (1) implies that the "average" transparency can be calculated from those of the thicker and thinner regions and it increases with the current density.…”

“…Equation (1) implies that the "average" transparency can be calculated from those of the thicker and thinner regions and it increases with the current density. If the junction has only a thinner barrier, (1) becomes simply (2), and the current density is 234…”

“…Improving their performance often requires increasing the critical current density to compensate for their high intrinsic capacitance [1], [2]. However, junctions with high current density have shown poor current-voltage characteristics, e.g., a large subgap leakage current, as observed in Nb/AlOx/Nb junctions [3].…”

Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx

“…In the AIST STP 2.5-kA/cm 2 [18], [19] and ADP2 10-kA/cm 2 processes [20], [21], the resistive layer RES1 is sandwiched inside isolation layer GC, which also separates the first metal layer/base electrode (BAS, or the M1 layer) from ground (GP, or the M0 layer). In layout, a via on layer GC connects BAS to GP, whereas a contact hole specified on layer RC connects BAS to RES1 through a part of the GC isolation.…”