CVD Filling of Narrow Deep 4H-SiC Trenches in a Quasi-Selective Epitaxial Growth Mode

Abstract

By mapping the source and HCl flow rates dependent growth rates, the evolving trend of a quasi-selective epitaxial growth (quasi-SEG) that growing very thin epilayer on mesa top and ensuring an extremely low risk of voids defect generation was firstly figured out on a 5-μm 4H-SiC trench. Then, basing on the acquired knowledge, a 25-μm 4H-SiC trench with an aspect ratio up to ~10 was completely filled in the quasi-SEG mode.

A Study of CVD Growth Parameters to Fill 50-μm-Deep 4H-SiC Trenches

“…The first demonstration of a SiC-SJ structure was verified on 6 μm p/n columns produced by MEG method using a two-rounds epitaxial growth and ion-implantation processes [4,5]. In addition, 25 μm p/n columns have been attained at a filling rate of 2.11 μm/h by the TFEG method in the quasi-selective epitaxial growth mode (quasi-SEG) [6], which fulfills the construction of a 3.3 kV SiC-SJ MOSFET. Nevertheless, applying this growth method for filling a 50-μm-deep trench for producing a SiC-SJ MOSFET with VB∼6.6 kV is thought to be unsatisfactory: the estimated filling rate on the 50-μm-deep trench will be about 1 μm/h, corresponding to an extremely long duration of ∼50 hours [6,7].…”

“…In addition, 25 μm p/n columns have been attained at a filling rate of 2.11 μm/h by the TFEG method in the quasi-selective epitaxial growth mode (quasi-SEG) [6], which fulfills the construction of a 3.3 kV SiC-SJ MOSFET. Nevertheless, applying this growth method for filling a 50-μm-deep trench for producing a SiC-SJ MOSFET with VB∼6.6 kV is thought to be unsatisfactory: the estimated filling rate on the 50-μm-deep trench will be about 1 μm/h, corresponding to an extremely long duration of ∼50 hours [6,7]. It is indicated that, the quasi-SEG mode, which focused on reducing the risk of void defects (trench closing) by pursuing the nearly zero growth on the mesa top, at the same time leads to a low filling rate which is unrealistic to fill a 50-μm-deep trench due to the extremely long duration.…”

Crystalline Quality Evaluation of SiC p/n Column Layers Formed by Trench-Filling-Epitaxial Growth

“…For high voltage class devices, thick alternating doping epitaxial layers have to be prepared and for which TFE growth is best suited. We have developed TFE growth to fabricate deep SJ structure and realized TFE growth with the thickness more than 50 μm, which is necessary for 6.5 kV-class SiC SJ devices [6]. Although TFE growth has different mechanism from normal epitaxial growth on flat substrates, crystalline quality of TFE layers hasn't been evaluated yet.…”