Cycle time optimization by timing driven placement with simultaneous netlist transformations

Abstract

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed.

Layout driven optimization of datapath circuits using arithmetic reasoning

“…Post-placement optimization followed by placement modifications [8], initial placement of an unmapped netlist followed by logic synthesis and final placement [5], integrating logic optimization into the inner loop of a placement algorithm [7] are among the most promising. However, most of these methods are based on traditional approaches for logic optimization and, hence, they achieve adequate results for control logic only.…”

“…Datapath circuits often form a significant part of a modern integrated circuit (IC), and in many cases the critical timing path of these ICs passes through them. Traditional logic synthesis techniques [1,5,7,8], which perform well on the control parts of the logic of the IC, are not well suited to optimize datapaths. Logic synthesis techniques based on algebraic optimizations are too limited to use the full spectrum of optimizations that are potentially available in datapaths due to the many existing symmetries.…”