We propose a multiple supply voltage scaling algorithm for low power designs. The algorithm combines a greedy approach and an iterative improvement optimization approach. In phase I, it simultaneously scales down as many gates as possible to lower supply voltages. In phase II, a multiple way partitioning algorithm is applied to further refine the supply voltage assignment of gates to reduce the total power consumption. During both phases, the timing correctness of the circuit is maintained. Level converters (LCs) are adjusted correctly according to the local connectivity of the different supply voltage driven gates. Experimental results show that the proposed algorithm can effectively convert the unused slack of gates into power savings. We use two of the ISPD2001 benchmarks and all of the ISCAS89 benchmarks as test cases. The 0.13-m CMOS TSMC library is used. On average, the proposed algorithm improves the power consumption of the original design by 42.5% with a 10.6% overhead in the number of LCs. Our study shows that the key factor in achieving power saving is including the most comportable supply voltage in the scaling process.

A partition-based IR drop-driven algorithm is proposed for standard cell placement. Different cost functions for reducing IR drop are used in the horizontal cut and vertical cut partitioning processes. In addition to minimizing the total wire length, we balance the power consumption of the two partitions during the horizontal cut partitioning process. During the vertical cut partitioning process, we move the cells with higher power consumption closer to the power sources to reduce the maximum IR drop of the row. After placement is finished, we apply a greedy placement refinement process to further reduce the value of the maximum IR drop. Each standard cell row is modeled with an equivalent conductance model. Then the IR drop of each row is calculated and analyzed. We compare the placement generated by the proposed approach with the wire length-driven placement. On average, the proposed approach improves the value of maximum IR drop by 51%. Therefore, it reduces the need to add power straps on the chip and more routing resources are saved.

Aiming at the security problems of network management,the paper describes the basic principle of PPPOE agreement based on the RouterOS. The paper shows that PPPOE services are realized by using RouterOS. At last combined with the application of the campus network of Huangshi Institute of Te chnology, gives out a PPPOE access program based on campus network . The conclusion demonstrate: the PPPOE using RouterOS could significantly improve the security of network well.

No abstract

No abstract