Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology

Yu, Hung-Chang; Lin, Kai-Chun; Lin, Ku-Feng; Huang, C.M.; Chih, Yu-Der; Ong, Tong-Chern; Chang, Jonathan; Natarajan, S.; Tran, L.C.

doi:10.1109/isscc.2013.6487710

Cited by 8 publications

(5 citation statements)

References 3 publications

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“…While encountering a power outage, these cells capture the SRAM contents in nonvolatile devices just before power loss and then restore the saved state when receiving power again. [76,77]; (e) a 12T-2R nvSRAM [19]; (f) a 1T-1R RRAM [21,54,78]; and (g) a 1T-1PCM PCM [22,79].…”

Section: Design Considerations For Nvm In Mcumentioning

confidence: 99%

“…Moreover, the decoupled read and write terminals facilitate the independent fine-tuning of the MTJ and SHE-metal dimensions, optimizing both readability and writability [64]. In the nvSRAM cell, M7 and M8 serve as extra access transistors that are disabled to separate the SHE-MTJs from the standard 6T SRAM [20]; (b) a 1FeFET FRAM [72][73][74][75]; (c) a 8T-2MTJ nvSRAM [64]; (d) a 1T-1MTJ MRAM [76,77]; (e) a 12T-2R nvSRAM [19]; (f) a 1T-1R RRAM [21,54,78]; and (g) a 1T-1PCM PCM [22,79].…”

Section: Design Considerations For Nvm In Mcumentioning

confidence: 99%

“…It also enables the concurrent writing of 0 or 1 states without needing to elevate BLs, enhancing write efficiency in MRAM. Figure 3f illustrates a 1T-1R bitcell occupying an area of 20 F 2 [54], which is more compact than earlier FRAM [89,90], STT-MRAM [16,76], and CBRAM [91,92] designs. The RRAM was equipped with a novel sense amplifier and a write-and-verify (WAV) voltage generator to increase the read and write yield.…”

Section: Design Considerations For Nvm In Mcumentioning

confidence: 99%

“…Figure 3. Bitcell structures of (a) a 6T-4C nvSRAM[20]; (b) a 1FeFET FRAM[72][73][74][75]; (c) a 8T-2MTJ nvSRAM[64]; (d) a 1T-1MTJ MRAM[76,77]; (e) a 12T-2R nvSRAM[19]; (f) a 1T-1R RRAM[21,54,78]; and (g) a 1T-1PCM PCM[22,79].…”

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confidence: 99%

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A Survey of Emerging Memory in a Microcontroller Unit

Qi,

Fan,

Cai

et al. 2024

Micromachines

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In the era of widespread edge computing, energy conservation modes like complete power shutdown are crucial for battery-powered devices, but they risk data loss in volatile memory. Energy autonomous systems, relying on ambient energy, face operational challenges due to power losses. Recent advancements in emerging nonvolatile memories (NVMs) like FRAM, RRAM, MRAM, and PCM offer mature solutions to sustain work progress with minimal energy overhead during outages. This paper thoroughly reviews utilizing emerging NVMs in microcontroller units (MCUs), comparing their key attributes to describe unique benefits and potential applications. Furthermore, we discuss the intricate details of NVM circuit design and NVM-driven compute-in-memory (CIM) architectures. In summary, integrating emerging NVMs into MCUs showcases promising prospects for next-generation applications such as Internet of Things and neural networks.

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Section: Design Considerations For Nvm In Mcumentioning

confidence: 99%

Section: Design Considerations For Nvm In Mcumentioning

confidence: 99%

Section: Design Considerations For Nvm In Mcumentioning

confidence: 99%

mentioning

confidence: 99%

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A Survey of Emerging Memory in a Microcontroller Unit

Qi,

Fan,

Cai

et al. 2024

Micromachines

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show abstract

“…3,11 F I G U R E 1 Hardware and software configuration for artificial intelligence (AI) Memory access occurs frequently in AI operations. However, nonvolatile memory including other materials, such as resistive RAM (ReRAM) 12 and magnetoresistive RAM (MRAM), 13 has poor write endurance. In principle, the proposed memory with OSFETs has excellent write endurance because data are rewritten by switching of transistors (as described in Section 7 below), implying CAAC-IGZO is a key technology to enable widespread practical applications of AI.…”

Section: Universal Memorymentioning

confidence: 99%

Crystalline IGZO ceramics (crystalline oxide semiconductor)–based devices for artificial intelligence

Yamazaki

Ohshita

Oota

et al. 2019

Int J Ceramic Engine & Sci

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In 2009, a crystalline oxide semiconductor with a layered structure, which we refer to as c‐axis–aligned crystalline indium‐gallium‐zinc oxide (CAAC‐IGZO), was first discovered. CAAC‐IGZO has a peculiar crystal structure in which clear grain boundaries are not observed despite high c‐axis alignment and absence of a‐b plane alignment. When compared to a Si field‐effect transistor (FET), a metal‐oxide‐semiconductor (MOS) FET, utilizing CAAC‐IGZO, presents lower off‐state current (on the order of yA [10−24 A]). These unique characteristics allow CAAC‐IGZO to realize devices with low power consumption. With the emerging era of artificial intelligence, wherein power saving becomes more significant, CAAC‐IGZO has attracted attention as a potential replacement for Si. This paper describes the characteristics and potentials of CAAC‐IGZO for the development of memory devices with unprecedented functions.

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WDBT: Non-volatile memory wear characterization and mitigation for DBT systems

Dong

Fang

et al. 2022

Journal of Systems and Software

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Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology

Cited by 8 publications

References 3 publications

A Survey of Emerging Memory in a Microcontroller Unit

A Survey of Emerging Memory in a Microcontroller Unit

Crystalline IGZO ceramics (crystalline oxide semiconductor)–based devices for artificial intelligence

WDBT: Non-volatile memory wear characterization and mitigation for DBT systems

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