DAG-aware circuit compression for formal verification

Bjesse, Per; Borälv, Arne

doi:10.1109/iccad.2004.1382541

Cited by 62 publications

(46 citation statements)

References 13 publications

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“…Our work on AIGs was motivated by fast compression of Boolean networks in formal verification [5]. We extended this method to work in synthesis, by making it delay-aware and replacing two-level structural matching of AIG subgraphs with functional matching of the subgraphs based on enumeration of 4-input cuts [26].…”

Section: Introductionmentioning

confidence: 99%

ABC: An Academic Industrial-Strength Verification Tool

Brayton

Mishchenko

2010

Lecture Notes in Computer Science

649

405

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Abstract. ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.

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Section: Introductionmentioning

confidence: 99%

ABC: An Academic Industrial-Strength Verification Tool

Brayton

Mishchenko

2010

Lecture Notes in Computer Science

649

405

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“…Further, depth is optimized by integrating AIG balancing using algebraic treeheight reduction [7] as part of the algorithm. The approach in [6] extends [8] which presents a similar rewriting algorithm that is applied in a top-down manner. The approach in [8] does not consider depth-preserving rewrites.…”

Section: Background a Related Workmentioning

confidence: 99%

“…The approach in [6] extends [8] which presents a similar rewriting algorithm that is applied in a top-down manner. The approach in [8] does not consider depth-preserving rewrites. In [9], the approach in [6] is extended to 5-input cuts.…”

Section: Background a Related Workmentioning

confidence: 99%

Optimizing Majority-Inverter Graphs With Functional Hashing

Soeken

Amarù

Gaillardon

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-A Majority-Inverter Graph (MIG) is a recently introduced logic representation form whose algebraic and Boolean properties allow for efficient logic optimization. In particular, when considering logic depth reduction, MIG algorithms obtained significantly superior synthesis results as compared to the state-of-the-art approaches based on AND-inverter graphs and commercial tools. In this paper, we present a new MIG optimization algorithm targeting size minimization based on functional hashing. The proposed algorithm makes use of minimum MIG representations which are precomputed for functions up to 4 variables using an approach based on Satisfiability Modulo Theories (SMT). Experimental results show that heavilyoptimized MIGs can be further minimized also in size, thanks to our proposed methodology. When using the optimized MIGs as starting point for technology mapping, we were able to improve both depth and area for the arithmetic instances of the EPFL benchmarks beyond the current results achievable by state-ofthe-art logic synthesis algorithms.

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“…In addition we work with constraints explicitly, a fact which entangles the cones of the objectives even more tightly. Finally, we do not use local BDDs [16] or AIG rewriting [5] to optimize the problem instance; instead we rely on saturation [24] and on learning from SSAT → to achieve a compact representation.…”

Section: Related Workmentioning

confidence: 99%

Implicative Simultaneous Satisfiability and Applications

Khasidashvili

Nadel

2012

Hardware and Software: Verification and Testing

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Abstract. This paper proposes an efficient algorithm for the systematic learning of implications. This is done as part of a new search and restart strategy in the SAT solver. We evaluate the new algorithm within a number of applications, including BMC and induction with invariant strengthening for equivalence checking. We provide extensive experimental evidence attesting to a speedup of one and often two orders of magnitude with our algorithm, on a representative set of industrial and publicly available test suites, as compared to a basic version of invariant strengthening. Moreover, we show that the new invariant strengthening algorithm alone performs better than induction and interpolation, and that the absolutely best result is achieved when it is combined with interpolation. In addition, we experimentally demonstrate the superiority of an application of our new algorithm to BMC.

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DAG-aware circuit compression for formal verification

Cited by 62 publications

References 13 publications

ABC: An Academic Industrial-Strength Verification Tool

ABC: An Academic Industrial-Strength Verification Tool

Optimizing Majority-Inverter Graphs With Functional Hashing

Implicative Simultaneous Satisfiability and Applications

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