DAG-aware logic synthesis of datapaths

Abstract

Traditional datapath synthesis for standardcell designs go through extraction of arithmetic operations from the high-level description, high-level synthesis, and netlist generation. In this paper, we take a fresh look at applying high-level synthesis methodologies in logic synthesis. We present a DAG-Aware synthesis technique for datapaths synthesis which is implemented using And-Inv-Graphs. Our approach targets area minimization. The proposed algorithm includes identifying vector multiplexers, searching for common specification logic, and reallocating multiplexers in the Boolean network. We propose an algorithm to identify common specification logic by using subgraph isomorphism. Experimental results show that our technique can provide over 10% area reduction beyond the traditional design flow. The proposed algorithm is tested on industry designs and academic benchmark suits using IBM 14nm technology.

Advanced datapath synthesis using graph isomorphism

“…Vector multiplexer is a set of 2-to-1 multiplexers with the identical control signals. First, they are collected by first structurally reverse engineering all the 2-to-1 multiplexers from gate-level netlist [7], and then being classified based on their control signals. Note that the multiplexers are eliminated from the collection if any of their data inputs has a fanout.…”

“…Recently, high-level optimization techniques, such as resource sharing, have been applied in logic synthesis to overcome some of the limitation of datapath synthesis for standard-cell designs. Specifically, a Directed Acyclic Graph (DAG) based logic synthesis technique that targets area minimization of datapath designs was proposed in [7]. It is a structural optimization technique implemented using And-Inv-Graphs (AIGs) [8], which offers bit-level resource sharing.…”

“…The most critical part of the technique is step 2, which solves the problems of identifying common logic and performing Boolean matching. In fact, finding isomorphism in AIG is a weighted graph isomorphism problem [7]. This is because, to represent an arbitrary Boolean network using AND nodes, the edges are required to represent inversion or a wire, which classifies an AIG as a weighted graph.…”

“…Although the technique of [7] offers new direction in datapath synthesis and promises area reduction, it has some limitations. First, the complexity of general graph isomorphism problem belongs to NP, but is not known if it is P or NP-complete.…”

“…3) The runtime complexity comparison between the AIG-based algorithm [7] and the one presented here is provided using illustrative examples (Section 3.1), and demonstrated using large datapath designs ( Figure 6).…”