Damage Evaluation of Wet-Chemical Si-Wafer Thinning/Backside Via Exposure Process

Abstract

To realize low-cost and damage-less through silicon via (TSV) formation, we evaluated the damage caused by a new wet-chemical Si-wafer thinning/backside via exposure process. Damage at the etched Si subsurface was examined using ballon-ring tests, cross-sectional transmission electron microscopy, and electron energy loss spectroscopy. The die fracture load obtained after this process was higher than those for processes that include a backgrinding step. There was little damage to the etched Si subsurface layer after our new process. We then evaluated the damage in 0.8-µm metal-oxide-semiconductor fieldeffect transistor generated by the new process. The changes in threshold voltage, subthreshold swing, transconductance, and leakage current were very small, even when the wafer was thinned down to 20 µm. Finally, we applied our new process to a Cu/Ta via wafer to evaluate the damage in a TSV. No damaged layers were observed in the TSV, and the leakage current between the TSVs after this process was sufficiently small for practical application. IndexTerms-Three-dimensional integrated circuit, three-dimensional integration, through silicon via, backside via exposure, Si wafer thinning, wet etching.

Edge Trimming Induced Defects on Direct Bonded Wafers

“…For this purpose, a "stress relief process" is utilized as a subsequent process after grinding, in particular, when the Si is thinner. Typical candidates used for this stress relief process are polishing [7,27], wet etching [28][29][30][31], and dry etching [5,31]. Although the damage removal of the ground surface has been comprehensively studied [16], the edge trimmed sidewall is not well done.…”

Modified Au/bulk Si eutectic bonding structure with reliable compatibility of KOH etching based on two-step local oxidation of silicon

“…On the one hand, based on the anisotropic etching property of KOH etching, the wafer-through V-shape grooves etched for packaged wafers are beneficial for the metal depositions when achieving the near-vertical metal interconnections [14]. On the other hand, KOH etching has been maturely utilized to exposure the raised metal-coated TSV bumps in via-first and via-mid flows after thinning by CMP [15]. Obviously, the combination of wafer bonding with KOH etching has been an essential strategy to bring about 3D integrated fabrications for devices, which necessitates the process compatibility of wafer bonding with KOH etching.…”