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To realize low-cost and damage-less through silicon via (TSV) formation, we evaluated the damage caused by a new wet-chemical Si-wafer thinning/backside via exposure process. Damage at the etched Si subsurface was examined using ballon-ring tests, cross-sectional transmission electron microscopy, and electron energy loss spectroscopy. The die fracture load obtained after this process was higher than those for processes that include a backgrinding step. There was little damage to the etched Si subsurface layer after our new process. We then evaluated the damage in 0.8-µm metal-oxide-semiconductor fieldeffect transistor generated by the new process. The changes in threshold voltage, subthreshold swing, transconductance, and leakage current were very small, even when the wafer was thinned down to 20 µm. Finally, we applied our new process to a Cu/Ta via wafer to evaluate the damage in a TSV. No damaged layers were observed in the TSV, and the leakage current between the TSVs after this process was sufficiently small for practical application. IndexTerms-Three-dimensional integrated circuit, three-dimensional integration, through silicon via, backside via exposure, Si wafer thinning, wet etching.

We proposed the wet-chemical Si wafer-thinning process and evaluated the damage caused by this process. For the damage evaluation, we measured the die fracture stress and fracture energy, and compared various wafer-thinning processes (backgrinding, wet-chemical Si wafer-thinning, backgrinding + chemical mechanical polishing, backgrinding + wet etching). The result of comparative study shows that wet-chemical wafer-thinning processing has very high fracture stress/energy demonstrating that the damage of wet-chemical Si wafer-thinning process is very small.

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