Wet-Chemical Silicon Wafer Thinning Process for High Chip Strength

Yoshikawa, Kunio; Miyazaki, Takumi; Watanabe, Naoya; Aoyagi, Masahiro

doi:10.1149/1.3700947

Cited by 4 publications

(2 citation statements)

References 11 publications

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“…The thinner the chip, the lower the possible bending radius [ 2 ]. Various groups published methods to achieve chip thicknesses between 10 µm and 50 µm and investigated their fracture strength after dicing [ 3 , 4 , 5 , 6 , 7 , 8 ]. The next step aiming towards high-quantity production of SiF is the automated assembly of ultrathin chips on flexible foil substrates.…”

Section: Introductionmentioning

confidence: 99%

Feasibility Study of an Automated Assembly Process for Ultrathin Chips

et al. 2020

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This paper presents a feasibility study of an automated pick-and-place process for ultrathin chips on a standard automatic assembly machine. So far, scientific research about automated assembly of ultrathin chips, with thicknesses less than 50 µm, is missing, but is necessary for cost-effective, high-quantity production of system-in-foil for applications in narrow spaces or flexible smart health systems applied in biomedical applications. Novel pick-and-place tools for ultrathin chip handling were fabricated and a process for chip detachment from thermal release foil was developed. On this basis, an adhesive bonding process for ultrathin chips with 30 µm thickness was developed and transferred to an automatic assembly machine. Multiple ultrathin chips aligned to each other were automatically placed and transferred onto glass and polyimide foil with a relative placement accuracy of ±25 µm.

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Section: Introductionmentioning

confidence: 99%

Feasibility Study of an Automated Assembly Process for Ultrathin Chips

et al. 2020

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“…At present, the cost TSV manufacturing is too high for it to be practical in most applications. This process, and the wet-chemical Si wafer-thinning process developed previously (13)(14)(15)(16), are expected to reduce the manufacturing costs of TSV.…”

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confidence: 99%

High-Speed Alkaline Etching for Backside Exposure of Through Silicon Vias

Yoshikawa

Miyazaki²,

Watanabe

et al. 2013

ECS Trans.

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We developed the high-speed alkaline etching of silicon for backside exposure of through silicon vias (TSVs). The spin etching rate of silicon was 2.1-6.6 μm/min when an accelerator was added to KOH solution. The etching rate ratio of silicon to Tetraethyl orthosilicate (TEOS) SiO2 was 66-125. We also applied KOH/accelerator solution to 8-inch Si (100) wafer with buried Cu/Ta vias. The most of buried Cu/Ta vias were uniformly exposed. The terraced structures were generated in the Si surface, although their step height was so small as to be negligible for practical application.

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