Damage free Ar ion plasma surface treatment on In0.53Ga0.47As-on-silicon metal-oxide-semiconductor device

Abstract

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In0.53Ga0.47As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In0.53Ga0.47As. The XPS spectra of Ar treated In0.53Ga0.47As show a decrease in the AsOx and GaOx signal intensities, and the MOSCAPs show higher accumulation capacitance (Cacc), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (Dit), which thereby led to a reduction in the threshold voltage (Vth) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.

Effect of HCl cleaning on InSb–Al2O3 MOS capacitors

“…Critically, when the ALD process temperature changed from 200 °C to 250 °C, a small change in flatband voltage was observed which, when accounting for the observations by Tereschenko et al, suggests that residual interfacial chlorine may be influencing the electrical characteristics of devices. This behaviour is of particular interest due to the uptake of HCl wet treatments in place of sulphidation treatments, [11][12][13][14] necessitating a more complete understanding of how HCl wet treatments influence surfaces and dielectric interfaces. As such, a study has been performed to investigate the role of InCl 3 on InSb MOS-CAPs, to ascertain whether an InCl 3 layer forms under normal processing conditions and whether it survives exposure to ambient oxygen; how quickly it desorbs as the temperature rises through the ALD process temperature window (150 °C-300 °C) and how the MOSCAP electrical behaviour changes as the InCl 3 layer is introduced and desorbed.…”

Effect of high-pressure deuterium annealing with high-κ stack onto In0.53Ga0.47As MOS capacitors on 300 mm Si substrate

“…Unlike the Si=SiO 2 interface, there exist large numbers of interface traps at the InGaAs gate stack, due to inability to perfectly eliminate various native oxides such as In-O x , Ga-O x , and As-O x . [10][11][12][13][14] As a remedy to passivate the interface of the InGaAs gate stacks, various methods have been investigated, including sulfur treatment, 15) As-decapping, 16) and H 2 annealing in the InGaAs gate stacks. 17,18) In Si MOSFETs, a D 2 high-pressure-annealing (HPA) has been reported to improve hot carrier reliability, lifetime improvement, and electrical performance at the Si-high-k interface, because D 2 tends to be easily incorporated at the Si=SiO 2 interface during the HPA step, and Si-D bonds are more resistant to hot-electron excitation than is the Si-H bond.…”