Damascene planar metal-insulator-metal tunnel junctions

Abstract

In this paper, we show a process for the fabrication of planar sub-attofarad capacitance metal-insulator-metal tunnel junctions with nanometer size. We show the engineering of the material stack, anti-diffusion barrier and electrode metal as well as the result of improved characteristics and stability in time of the devices. This engineering is supported by a simulation tool we developed and its goal is to optimize the original process for the development of high-temperature operating SETs and other innovative nanoelectronic devices.

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

“…The MIM junction is the building block of the different nanoelectronic devices proposed in this paper, and the MIM oxide capacitors that are essential passive devices widely used in the microelectronic industry integrated circuit fabrication. They can be exploited for more fundamental research purposes such as dielectric or dielectric stacking [8,9] permittivity and barrier height extraction at the nanometer scale. Finally, as it will be shown here, they are excellent devices to evaluate the effect of the fabrication procedure, materials, and deposition methods on the junction and characterize its aging and performance before using it in a circuit.…”

“…However, instead of the two tunnel junctions, one wants to obtain a single dielectric junction. Therefore, the first metal electrode goes all the way to the contact [9].…”