DAPPER: Data Aware Approximate NoC for GPGPU Architectures

Raparti, Venkata Yaswanth; Pasricha, Sudeep

doi:10.1109/nocs.2018.8512159

Cited by 23 publications

(11 citation statements)

References 22 publications

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“…Approximate storage is often for larger capacity for high-density image storage [27][28][29][30]. 3 [31] and network on chip architectures [32][33][34][35][36] are proposed for higher network throughput using the critical feature of data type information or dual scaling voltage.…”

Section: Approximate Techniquesmentioning

confidence: 99%

“…This approximate computing paradigm can be applied in different components of application-specified accelerators with different quality-power (or performance) tradeoffs at different abstractions layers [2]. There have been a variety of approximate techniques proposed for gaining power saving or performance improvement, which cover all the sites in approximate computing [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], approximate storage [18][19][20][21][22][23][24][25][26][27][28][29][30], and approximate communication [31][32][33][34][35][36]. How to utilize these approximate techniques is a significant issue for designing a cost-effective approximate accelerator.…”

Section: Introductionmentioning

confidence: 99%

“…It calculates the output quality of approximate configuration with a few formulas very quickly. However, these analytical models are usually limited to certain approximate sites such as approximate adders or approximate multipliers for calculation [40,41], approximate SRAM/DRAM/SSD/PCM [42][43][44][45] for storage, and approximate data transmission for communication [31][32][33][34][35][36]. Particularly, there are a variety of accuracy-power/performance tradeoffs for a specified approximate component.…”

Section: Introductionmentioning

confidence: 99%

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HEAP: A Holistic Error Assessment Framework for Multiple Approximations Using Probabilistic Graphical Models

Jiao

2020

Electronics

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Approximate computing has been a good paradigm of energy-efficient accelerator design. Accurate and fast error estimation is critical for appropriate approximate techniques selection so that power saving (or performance improvement) can be maximized with acceptable output quality in approximate accelerators. In the paper, we propose HEAP, a Holistic Error assessment framework to characterize multiple Approximate techniques with Probabilistic graphical models (PGM) in a joint way. HEAP maps the problem of evaluating errors induced by different approximate techniques into a PGM issue, including: (1) A heterogeneous Bayesian network is represented by converting an application’s data flow graph, where various approximate options are {precise, approximate} two-state X*-type nodes, while input or operating variables are {precise, approximate, unacceptable} three-state X-type nodes. These two different kinds of nodes are separately used to configure the available approximate techniques and track the corresponding error propagation for guaranteed configurability; (2) node learning is accomplished via an approximate library, which consists of probability mass functions of multiple approximate techniques to fast calculate each node’s Conditional Probability Table by mechanistic modeling or empirical modeling; (3) exact inference provides the probability distribution of output quality at three levels of precise, approximate, and unacceptable. We do a complete case study of 3 × 3 Gaussian kernels with different approximate configurations to verify HEAP. The comprehensive results demonstrate that HEAP is helpful to explore design space for power-efficient approximate accelerators, with just 4.18% accuracy loss and 3.34 × 105 speedup on average over Mentor Carlo simulation.

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Section: Approximate Techniquesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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HEAP: A Holistic Error Assessment Framework for Multiple Approximations Using Probabilistic Graphical Models

Jiao

2020

Electronics

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“…These applications and designs accentuate acceptable inaccuracy of communication and computation. Many approaches, such as APPROX-NoC [13], ABDTR [14] and DAPPER [19], have explored lossy communication in NoCs and achieve a good latency reduction and power saving. These approximation designs show that applications have a sufficient amount of value similarities, and data traversing the network have sufficient capacity to be approximated.…”

Section: B Lossy Communication Is Acceptablementioning

confidence: 99%

An Approximate Bufferless Network-on-Chip

Wang

2019

IEEE Access

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Bufferless network-on-chip (NoC) designs have drawn research attention in massively parallel multicore systems via their significant benefits in power and area savings. However, it shows poor throughput and low bandwidth in current bufferless designs due to complex bufferless routing and arbitration. Especially in the NACK-based bufferless network, the network performance will be affected significantly as the network conflicts increased caused by packet retransmissions. To this end, we proposed a novel approximate bufferless network, ABNoC. ABNoC lessens network conflicts and packet retransmissions via an approximate allocation mechanism (AAM) and a packet approximation method. We show that, compared with SCARAB, ABNoC improved the bandwidth up to 1.92 times and achieved 1.2 times faster in runtime. Besides, ABNoC accomplished 83.6% retransmission reduction and 46.7% latency reduction, while maintaining low application error.INDEX TERMS Network-on-chip, bufferless NoC, approximate allocation, packet approximation.

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“…With the rise in number of processing cores and growing parallelism in applications, the communication traffic in a manycore processor has been increasing. Chip designers and manufacturers are moving towards network-on-chip (NoC) as their de-facto intra-chip communication fabric [1]- [2]. Typically, emerging manycore processors have tens to hundreds of components that are designed either by in-house engineers or obtained from third-party vendors (3PIP), and then finally integrated together in a single global facility.…”

Section: Introductionmentioning

confidence: 99%

Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing

Raparti

Pasricha

2019

Proceedings of the 56th Annual Design Automation Conference 2019

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Data-snooping is a serious security threat in NoC fabrics that can lead to theft of sensitive information from applications executing on manycore processors. Hardware Trojans (HTs) covertly embedded in NoC components can carry out such snooping attacks. In this paper, we first describe a low-overhead snooping invalidation module (SIM) to prevent malicious data replication by HTs in NoCs. We then devise a snooping detection module (THANOS) to also detect malicious applications that utilize such HTs. Experimental analysis shows that unlike state-of-theart mechanisms, SIM and THANOS not only mitigate snooping attacks but also improve NoC performance by 48.4% in the presence of these attacks, with a minimal ~2.15% area and ~5.5% power overhead.

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DAPPER: Data Aware Approximate NoC for GPGPU Architectures

Cited by 23 publications

References 22 publications

HEAP: A Holistic Error Assessment Framework for Multiple Approximations Using Probabilistic Graphical Models

HEAP: A Holistic Error Assessment Framework for Multiple Approximations Using Probabilistic Graphical Models

An Approximate Bufferless Network-on-Chip

Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing

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