Dark silicon management: an integrated and coordinated cross-layer approach

Pagani, Santiago; Bauer, Lars; Chen, Qingqing; Glocker, Elisabeth; Hannig, Frank; Herkersdorf, Andreas; Khdr, Heba; Pathania, Anuj; Schlichtmann, Ulf; Schmitt‐Landsiedel, D.; Sagi, Mark; Sousa, Ericles; Wagner, Philipp; Wenzel, Volker; Wild, Thomas; Henkel, Jörg

doi:10.1515/itit-2016-0028

Cited by 5 publications

(3 citation statements)

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“…However, information can still flow over physical channels such as heat dissipation, system load, cache-hit rates or network congestion, which can be queried by resource-aware programs and which endanger C. Such side channels can be further avoided through stronger spatial isolation, in which, for example, a set of unused processing elements or memory banks is left free between two applications on a tile. These buffer zones correspond to "physical borderlines" (or "dark resources") that further decrease the potential of side channels such as heat dissipation [22]. A sensitive application may even ask the run-time system to grant exclusive access to an entire tile.…”

Section: Constructive Measuresmentioning

confidence: 99%

Providing security on demand using invasive computing

Drescher

Erhardt

Freiling

et al. 2016

It - Information Technology

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Section: Constructive Measuresmentioning

confidence: 99%

Providing security on demand using invasive computing

Drescher

Erhardt

Freiling

et al. 2016

It - Information Technology

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show abstract

“…Higher peak power also results in higher on-chip temperatures, which leads to reliability issues [2][3][4]. Higher temperatures can also trigger performance crippling thermal-throttling, which makes execution unpredictable [5]. We can minimize peak power by executing all of the tasks sequentially on a single core, but such an execution will violate the deadline.…”

Section: Introductionmentioning

confidence: 99%

PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications

Maity

Pathania

Mitra

2020

JLPEA

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Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak power consumption. Parallel execution of multiple tasks on multiple cores results in a quicker execution, but higher peak power. Peak power single-handedly determines the involved cooling costs in many-cores, while its violations could induce performance-crippling execution uncertainties. Less task parallelization, on the other hand, results in lower peak power, but a more prolonged deadline violating execution. The problem of peak power minimization in many-cores is to determine task-to-core mapping configuration in the spatio-temporal domain that minimizes the peak power consumption of an application, but ensures application still meets the deadline. All previous works on peak power minimization for many-core applications (with or without DAG) assume only single-threaded tasks. We are the first to propose a framework, called PkMin, which minimizes the peak power of many-core applications with DAG that have multi-threaded tasks. PkMin leverages the inherent convexity in the execution characteristics of multi-threaded tasks to find a configuration that satisfies the deadline, as well as minimizes peak power. Evaluation on hundreds of applications shows PkMin on average results in 49.2% lower peak power than a similar state-of-the-art framework.

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“…First of all, power and temperature management have to perform dynamic voltage and frequency scaling or power gating of processing elements to stay within the thermal design power, as described in [16] (which is also part of this special issue). Furthermore, hardware faults might occur more often thus making resources temporally or, due to manufacturing variability and aging, even permanently unavailable (cf.…”

Section: Introductionmentioning

confidence: 99%

Invasive computing for timing-predictable stream processing on MPSoCs

Wildermann

Bäder

Bauer

et al. 2016

It - Information Technology

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Multi-Processor Systems-on-a-Chip (MPSoCs) provide sufficient computing power for many applications in scientific as well as embedded applications. Unfortunately, when real-time requirements need to be guaranteed, applications suffer from the interference with other applications, uncertainty of dynamic workload and state of the hardware. Composable application/architecture design and timing analysis is therefore a must for guaranteeing real-time applications to satisfy their timing requirements independent from dynamic workload. Here, Invasive Computing is used as the key enabler for compositional timing analysis on MPSoCs, as it provides the required isolation of resources allocated to each application. On the basis of this paradigm, this work proposes a hybrid application mapping methodology that combines designtime analysis of application mappings with run-time management. Design space exploration delivers several resource reservation configurations with verified real-time guarantees for individual applications. These timing properties can then be guaranteed at run-time, as long as dynamic resource allocations comply with the offline analyzed resource configurations. This article describes our methodology and presents programming, optimization, analysis, and hardware techniques for enforcing timing predictability. A case study illustrates the timing-predictable management of real-time computer vision applications in dynamic robot system scenarios.

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Dark silicon management: an integrated and coordinated cross-layer approach

Cited by 5 publications

References 0 publications

Providing security on demand using invasive computing

Providing security on demand using invasive computing

PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications

Invasive computing for timing-predictable stream processing on MPSoCs

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