Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

Abstract

The synthesis of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of today's sophisticated VLSI circuits, and a number of efficient algorithms have been proposed in the literature for this purpose. The subject paper reports new techniques that facilitate designing such space-efficient BIST support circuits using knowledge of compact test sets, with the target objective of minimizing the storage requirements for the circuit under test (CUT), while retaining the fault coverage information as best as possible. The suggested techniques take advantage of some well-known concepts of conventional switching theory, particularly those of cover table and frequency ordering, as commonly utilized in the minimization of switching functions, in conjunction with a new measure of failure probability in case of stochastic dependence of line errors, besides knowledge of Hamming distance, sequence weights, and derived sequences as previously used by the authors in sequence characterization, in the selection of specific logic gates for merger of an arbitrary number of output bit streams from the CUT. The outputs coming out of the space compactor may eventually be fed into a time compactor to derive the CUT signatures. The developed techniques guarantee good design with high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are provided in the paper, and the simplicity and ease of their implementations are demonstrated with various examples. In particular, the paper gives results on extensive simulation runs on the ISCAS 85 combinational benchmark circuits with ATALANTA, FSIM, and COMPACTEST programs which confirm the merit of the approaches under conditions of both stochastic independence and dependence of multiple line output errors. A performance comparison of the designed space compactors with conventional linear parity tree space compactors as benchmark is also provided, which demonstrates the enhanced tradeoff for the new circuits in terms of fault coverage and the CUT resources consumed in comparison with the existing design methodologies.

Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

“…Some of the common space compression techniques include the parity tree space compaction, hybrid space compression, dynamic space compression, quadratic functions compaction, programmable space compaction, and cumulative balance testing. The parity tree compactor circuits [36], [39], [46], [49], [50] are composed of only XOR gates. An XOR gate has very good signal-to-error propagation properties that are quite desirable for space compression.…”

“…The basic theme of the approaches proposed is to select appropriate logic gates to merge two candidate output lines of the CUT under conditions of stochastic independence and dependence of single and double line errors, using sequence characterization and other concepts introduced by the authors. However, the criteria of selecting a number of CUT output lines for optimal generalized sequence mergeability were also developed and utilized in the design of space compression networks, based on stochastic independence of multiple line errors, and also on stochastic dependence of multiple line errors using the concept of generalized detectable or missed error probability estimates [46], [50], [57], with extensive simulations conducted with ATALANTA, FSIM, and COM PACTEST [59], [61], [62]; however, optimal generalized sequence mergeability is not the concern of this paper, and as such is not discussed .…”