Data-dependent logic swing internal bus architecture for ultralow-power LSI's

Hiraki, M.; Kojima, Hirotsugu; Misawa, H.; Akazawa, Takashi; Hatano, Yuji

doi:10.1109/4.375959

Cited by 47 publications

(14 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The reduced swing communication suffers from reduced signal to noise ratio, especially as the supply voltages are scaled down [9][10][11][12]. The coding of data has been used for reducing power dissipation through the reduction of correlated and self-transitions.…”

Section: Figure1mentioning

confidence: 99%

Bus encoding scheme to eliminate unwanted signal transitions

Elkammar

Scheinberg

Vemuru

2006

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

View full text Add to dashboard Cite

As the technology scales down, the increased wire aspect ratio and the reduced spacing between the individual wires within a bus result in increased crosscoupling capacitances. This increases crosstalk noise and power dissipation particularly in wide data buses. We propose an efficient encoding scheme that eliminates correlated switching (coupling transitions) in 4-bit busses and also minimizes self-transitions among the wires in these data busses. Wider data busses are implemented using these 4-bit bus blocks.

show abstract

Section: Figure1mentioning

confidence: 99%

Bus encoding scheme to eliminate unwanted signal transitions

Elkammar

Scheinberg

Vemuru

2006

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

View full text Add to dashboard Cite

show abstract

“…Charge Inter-Shared Bus (CISB) [3] and Charge Recycling Bus (CRB) [4] are two schemes to reduce the interconnect swing by charge sharing among multiple data bit lines of a bus. Both of them can suppress the interconnect swing by a factor of n (where n is the number of bits), while the Charging Recyling Bus can produce quadratic power savings with a factor of n 2 .…”

Section: Low Swing Busmentioning

confidence: 99%

“…Short of reducing the average length of the wires and their fanout by using advanced processes or improved architectures, reducing the voltage swing of the signal on the wire is the best bet towards getting better energy efficiency. In this paper, we will analyze the effectiveness of a number of reduced swing interconnect schemes that have been proposed in the literature [2][3][4][5][6]. In addition, a number of novel or modified circuits will be introduced, simulated, and critiqued.…”

mentioning

confidence: 99%

Low-swing interconnect interface circuits

Zhang

Rabaey

1998

Proceedings of the 1998 International Symposium on Low Power Electronics and Design - ISLPED '98

View full text Add to dashboard Cite

This paper reviews a number of low-swing onchip interconnect schemes, and presents a thorough analysis of their effectiveness and limitations. In addition, several new interface circuits, presenting even more energy savings, are proposed. Some of these circuits not only reduce the interconnect swing, but also use very low supply voltages, so as to obtain quadratic energy savings. The performances of each of the presented circuits are thoroughly examined using simulation on a benchmark interconnect circuit. Energy savings with a factor of seven have been observed for some of the schemes. INTRODUCTIONIn the deep-submicron era, interconnect wires (and the associated driver and receiver circuits) are responsible for an ever increasing fraction of the energy consumption of an integrated circuit. Most of this increase is due to global wires, such as busses and clock and timing signals. This observation is particularly true for reconfigurable circuits. For instance, it has been observed that more than 90% of the power dissipation of traditional FPGA components (over a wide range of applications) is due to the interconnect [1]. For gate array and cell library based designs, Dake Liu [8] found that the power consumption of wires and clock signals can be up to 40% and 50% of the total on-chip power consumption respectively. Obviously, techniques that can help to reduce these ratios are very desirable. Short of reducing the average length of the wires and their fanout by using advanced processes or improved architectures, reducing the voltage swing of the signal on the wire is the best bet towards getting better energy efficiency. In this paper, we will analyze the effectiveness of a number of reduced swing interconnect schemes that have been proposed in the literature [2][3][4][5][6]. In addition, a number of novel or modified circuits will be introduced, simulated, and critiqued. To present a fair and realistic base for comparison, a single test circuit will be used. Overall, it is found that the proposed schemes present a wide range of potential energy reductions, yet that other considerations such as complexity, reliability, and performance play important roles as well.The paper is organized as follows. In section 3, the test bed that will be used in all simulations is presented. This is followed by a review and comparison of a number of architectures, obtained from the open literature. Several novel or modified low-swing schemes are proposed and analyzed in section 5. Finally, section 6 brings them all together and draws some conclusions. TEST ARCHITECTURE AND QUALITY METRICSPresenting a fair comparison for the various interconnect schemes that are presented in this paper requires a common and fair test-bed. Fig. 1(a) illustrates the schematic of our benchmark interconnect circuit. The driver converts a fullswing input into a reduced-swing interconnect signal, which is converted back to a full-swing output by the receiver. The interconnect line is a metal-3 layer wire with a length of 10 mm, modeled by a π3 dis...

show abstract

“…This in turn increases the delay spread (differences in delay) among these buses. The low swing bus design in [5,6,7] uses a single supply voltage (V swing < V dd ) for all interconnects irrespective of their individual capacitances and hence, the delay spread can not be reduced.…”

Section: Introductionmentioning

confidence: 99%

“…As shown in equation (1), the power consumption is proportional to the voltage swing of interconnects. Hence, to reduce the power consumption due to interconnect, low swing buses have been used [5,6,7].…”

Section: Introductionmentioning

confidence: 99%

Adaptive supply voltage technique for low swing interconnects

Jeong¹,

Paul²,

Roy³

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

View full text Add to dashboard Cite

-The increase in power consumption due to interconnects and the variation in delays (delay spread) among long interconnects are becoming important issues for design of high performance and low power circuits in scaled technologies. In this paper we propose an adaptive supply voltage technique for low swing interconnects. The proposed technique assigns different supply voltages to drive interconnects based on their delay. The voltage assignment is done only once during the initialization period of the circuit. Hence, there is no extra power consumption in the active mode. We also show that there is an optimum number of supply voltages required to achieve maximum power saving. Simulation results show that for a set of 64 buses we can achieve 42.8% and 55.9% reductions in the power consumption and delay spread, respectively.

show abstract

Data-dependent logic swing internal bus architecture for ultralow-power LSI's

Cited by 47 publications

References 6 publications

Bus encoding scheme to eliminate unwanted signal transitions

Bus encoding scheme to eliminate unwanted signal transitions

Low-swing interconnect interface circuits

Adaptive supply voltage technique for low swing interconnects

Contact Info

Product

Resources

About