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As CMOS technology reaches its physical limits, new technologies such as Quantum-dot Cellular Automata (QCA), Single Electron Tunneling (SET) and Tunneling Phase Logic (TPL) are being proposed as alternatives to CMOS technology. These technologies use either majority or minority logic to implement logic functions. Existing majority/minority logic synthesis methods, based on three-feasible networks, often result in sub-optimal solutions. In this paper, an efficient algorithm to find the minimal majority gate mapping, along with a Majority expression Look-Up Table (MLUT) is developed. Based on the MLUT, a comprehensive majority/minority logic synthesis technique is proposed. A redundancy removal method is also developed to further optimize the synthesized circuit. This technique makes effort towards achieving different optimization goals and results in fewer majority gates and fewer levels than previous methods. For the 29 MCNC benchmark circuits, when targeted to optimize the logic levels, there is an average reduction of 7.0% in the number of levels as well as 6.3% in the number of gates. For optimization targeted to reduce gate counts, there is an average reduction of 9.5% in the number of gates as well as 0.8% in the number of levels, as compared to the best available method.Index Terms -logic synthesis, majority gates, quantum-dot cellular automata (QCA) 

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Simultaneous switching noise (SSN) on power supply lines is caused by the large switching transient currents flowing through parasitic inductances at the chip-package-pin interface. A new expression to estimate SSN in CMOS circuits that includes the velocity saturation effects seen in the short-channel MOSFET's is derived. SPICE Level 3 simulation results show that the formula predicts the SSN more accurately as compared to existing approaches for submicron processes even at reduced supply voltages.