Proceedings of the 15th International Symposium on System Synthesis - ISSS '02 2002
DOI: 10.1145/581199.581245
|View full text |Cite
|
Sign up to set email alerts
|

Data memory design considering effective bitwidth for low-energy embedded systems

Abstract: This paper presents a novel low-energy memory design technique, considering effective bitwidth of variables for applicationspecific systems, called VAbM technique. It targets the exploitation of both data locality and effective bitwidth of variables to reduce energy consumed by redundant bits. Under constraints of the number of memory banks, the VAbM technique use variable analysis results to perform allocating and assigning on-chip RAM into multiple memory banks, which have different size with different numbe… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2003
2003
2010
2010

Publication Types

Select...
3
2
2

Relationship

1
6

Authors

Journals

citations
Cited by 27 publications
(2 citation statements)
references
References 12 publications
0
2
0
Order By: Relevance
“…DISCUSSION OF RELATED WORK Prior work on memory design for embedded systems focused on several aspects, including scratch-pad memory partitioning [1,16], cache partitioning [15], general memory design issues [3,13], and hierarchy design [4]. Meftali et al [9] considered the memory allocation problem, which they formulate based on an integer linear programming model.…”
Section: Methodsmentioning
confidence: 99%
“…DISCUSSION OF RELATED WORK Prior work on memory design for embedded systems focused on several aspects, including scratch-pad memory partitioning [1,16], cache partitioning [15], general memory design issues [3,13], and hierarchy design [4]. Meftali et al [9] considered the memory allocation problem, which they formulate based on an integer linear programming model.…”
Section: Methodsmentioning
confidence: 99%
“…[8] discussed bitwidth analysis with application to silicon compilation and reduced silicon real estate by 15-86%, improved clock speed by 3-249%, and reduced power by 46-73%. [9] presented datapath optimization for power minimization and [10] presented low-energy memory design considering bitwidth. [6] discussed dynamically exploiting narrow width operands to improve processor power and performance.…”
Section: Introductionmentioning
confidence: 99%