Data of multilayer mesh NoC performance analysis for throughput and delay over FTP and CBR applications

Panem, Charanarur; Rane, Udaysign V.; Gad, Rajendra S.

doi:10.1016/j.dib.2022.108196

Cited by 1 publication

(1 citation statement)

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“…A constant bandwidth network ensures that a portion of the data flow has constant average bandwidth. Hard real-time networks ensure that the maximum packet transmission delay of a part of the data flow is less than a hard deadline [21]. Soft realtime networks guarantee that the average transmission delay of a portion of the data stream is less than a predetermined deadline.…”

Section: Quality Of Servicementioning

confidence: 99%

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Nagalaxmi

Rao²,

P.Chandrasekar

2022

JICS

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Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

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Section: Quality Of Servicementioning

confidence: 99%