Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Abstract

Abstract-Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age -the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

“…We use the read-retry operation present within MLC NAND flash devices to accurately read the cell threshold voltage [3,4,6,29]. As threshold voltage values are proprietary information, we present our results using a normalized threshold voltage, where the nominal value of V pass is equal to 512 in our normalized scale, and where 0 represents GND.…”

“…However, as its capacity increases, flash memory suffers from different types of circuitlevel noise, which greatly impact its reliability. These include program/erase cycling noise [2,3], cell-to-cell program interference noise [2,5,8], retention noise [2,4,6,7,23,24], and read disturb noise [11,14,24,33]. Among all of these types of noise, read disturb noise has largely been understudied in the past for MLC NAND flash, with no open-literature work available today that characterizes and analyzes the read disturb phenomenon.…”

“…V pass Tuning extends flash endurance by exploiting the finding that a lower V pass reduces the read disturb error count (Sec. 4). Second, we propose Read Disturb Recovery (RDR), a mechanism that exploits the differences in the susceptibility of different cells to read disturb to extend the effective correction capability of error-correcting codes (ECC).…”

Error Analysis and Adaptable Error-correct Scheme for NAND Flash Memory

“…In NAND flash memory cells, the electric charges trapped in tunnel oxide can be de-trapped over time [8]. The decrease of charges can cause the changing of the flash cell threshold voltage, which can directly result in flash errors.…”

Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory

“…However, this method requires the additional cell area overhead of NAND flash-memory due to the additional flags which depend on the code length of the data unit. The optimal read reference voltage method during the P/E cycle lifetime of 2y-nm MLC flash-memory was proposed in [12]. This method demonstrated significant benefits in raw bit error rate (RBER) reduction, flash life time extension and reduction in flash read latency.…”