Data tiering in heterogeneous memory systems

Dulloor, Subramanya R.; Roy, Ahin; Zhao, Zheguang; Sundaram, Narayanan; Satish, Nadathur; Sankaran, Rajesh; Jackson, Jeff; Schwan, Karsten

doi:10.1145/2901318.2901344

Cited by 156 publications

(85 citation statements)

References 30 publications

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“…Managing hybrid memory or storage Many generic systems manage hybrid memory and storage. X-mem automatically places application data based on application execution patterns [19]. Thermostat transparently migrates memory pages between DRAM and NVM while considering page granularity and performance [3].…”

Section: Related Workmentioning

confidence: 99%

StreamBox-HBM

Miao¹,

Jeon²,

Pekhimenko³

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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Stream analytics has an insatiable demand for memory and performance. Emerging hybrid memories combine commodity DDR4 DRAM with 3D-stacked High Bandwidth Memory (HBM) DRAM to meet such demands. However, achieving this promise is challenging because (1) HBM is capacitylimited and (2) HBM boosts performance best for sequential access and high parallelism workloads. At first glance, stream analytics appears a particularly poor match for HBM because they have high capacity demands and data grouping operations, their most demanding computations, use random access.This paper presents the design and implementation of StreamBox-HBM, a stream analytics engine that exploits hybrid memories to achieve scalable high performance.StreamBox-HBM performs data grouping with sequential access sorting algorithms in HBM, in contrast to random access hashing algorithms commonly used in DRAM. StreamBox-HBM solely uses HBM to store Key Pointer Array (KPA) data structures that contain only partial records (keys and pointers to full records) for grouping operations. It dynamically creates and manages prodigious data and pipeline parallelism, choosing when to allocate KPAs in HBM. It dynamically optimizes for both the high bandwidth and limited capacity of HBM, and the limited bandwidth and high capacity of standard DRAM.StreamBox-HBM achieves 110 million records per second and 238 GB/s memory bandwidth while effectively utilizing all 64 cores of Intel's Knights Landing, a commercial server with hybrid memory. It outperforms stream engines with sequential access algorithms without KPAs by 7× and stream engines with random access algorithms by an order Permission to make digital of magnitude in throughput. To the best of our knowledge, StreamBox-HBM is the first stream engine optimized for hybrid memories.

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Section: Related Workmentioning

confidence: 99%

StreamBox-HBM

Miao¹,

Jeon²,

Pekhimenko³

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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“…The results show that although the average response time of I/O accesses is decreased, the migration algorithm needs to be adapted as the migration overhead is considerably smaller between DIMM and SSDs than between SSDs and HDDs. A different approach is to determine automatically whether a given memory area can benefit from DRAM characteristics by using a profiling tool [18]. Furthermore, NOVA is a file system aiming to increase the performance and offering strong consistency guarantees at the same time through additional metadata structures held in DRAM, accelerating the lookup.…”

Section: Acceleratorsmentioning

confidence: 99%

Survey of Storage Systems for High-Performance Computing

Lüttgau

Kuhn

Duwe

et al. 2018

JSFI

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In current supercomputers, storage is typically provided by parallel distributed file systems for hot data and tape archives for cold data. These file systems are often compatible with local file systems due to their use of the POSIX interface and semantics, which eases development and debugging because applications can easily run both on workstations and supercomputers. There is a wide variety of file systems to choose from, each tuned for different use cases and implementing different optimizations. However, the overall application performance is often held back by I/O bottlenecks due to insufficient performance of file systems or I/O libraries for highly parallel workloads. Performance problems are dealt with using novel storage hardware technologies as well as alternative I/O semantics and interfaces. These approaches have to be integrated into the storage stack seamlessly to make them convenient to use. Upcoming storage systems abandon the traditional POSIX interface and semantics in favor of alternative concepts such as object and key-value storage; moreover, they heavily rely on technologies such as NVM and burst buffers to improve performance. Additional tiers of storage hardware will increase the importance of hierarchical storage management. Many of these changes will be disruptive and require application developers to rethink their approaches to data management and I/O. A thorough understanding of today's storage infrastructures, including their strengths and weaknesses, is crucially important for designing and implementing scalable storage systems suitable for demands of exascale computing.

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“…Other researchers have proposed to mitigate long SCM latencies by using conventional planar DRAM DIMMs for hardware-managed caches [59], OS-based page migration [29] and application-assisted data placement [20]. Applying these designs in the context of server workloads will expose the lack of internal parallelism in planar DRAM devices [72], leading to excess request queuing and therefore inflated latencies.…”

Section: Related Workmentioning

confidence: 99%

“…DRAM and SCM flat integration. While we considered a twolevel hierarchy with a hardware-managed DRAM cache as our baseline ( §3), a number of prior proposals consider an alternative memory system organization: flat integration of SCM and DRAM on a shared memory bus [1,20,29]. In these proposals, software is responsible for placing the data on the heterogeneous DIMMs, relying on heuristics to optimize for performance [1,20] or energy efficiency [29].…”

Section: Related Workmentioning

confidence: 99%

Design guidelines for high-performance SCM hierarchies

Ustiugov¹,

Daglis²,

Picorel

et al. 2018

Proceedings of the International Symposium on Memory Systems

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With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few factors of DRAM. Nevertheless, the latency-sensitive nature of memory-resident services makes seamless integration of SCM in servers questionable. In this paper, we ask the question of how best to introduce SCM for such servers to improve overall performance/cost over existing DRAM-only architectures. We first show that even with the most optimistic latency projections for SCM, the higher memory access latency results in prohibitive performance degradation. However, we find that deployment of a modestly sized high-bandwidth 3D stacked DRAM cache makes the performance of an SCM-mostly memory system competitive. The high degree of spatial locality that memory-resident services exhibit not only simplifies the DRAM cache's design as page-based, but also enables the amortization of increased SCM access latencies and the mitigation of SCM's read/write latency disparity.We identify the set of memory hierarchy design parameters that plays a key role in the performance and cost of a memory system combining an SCM technology and a 3D stacked DRAM cache. We then introduce a methodology to drive provisioning for each of these design parameters under a target performance/cost goal. Finally, we use our methodology to derive concrete results for specific SCM technologies. With PCM as a case study, we show that a two bits/cell technology hits the performance/cost sweet spot, reducing the memory subsystem cost by 40% while keeping performance within 3% of the best performing DRAM-only system, whereas single-level and triple-level cell organizations are impractical for use as memory replacements.• Information systems → Storage class memory; Cloud based storage; • Hardware → Memory and dense storage; KEYWORDS Storage-class memory, heterogeneous memory hierarchy, 3D stacked DRAM ACM Reference Format:

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Data tiering in heterogeneous memory systems

Cited by 156 publications

References 30 publications

StreamBox-HBM

StreamBox-HBM

Survey of Storage Systems for High-Performance Computing

Design guidelines for high-performance SCM hierarchies

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