Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture 2011
DOI: 10.1145/2155620.2155628
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Dataflow execution of sequential imperative programs on multicore architectures

Abstract: As multicore processors become the default, researchers are aggressively looking for program execution models that make it easier to use the available resources. Multithreaded programming models that rely on statically-parallel programs have gained prevalence. Most of the existing research is directed at adapting and enhancing such models, alleviating their drawbacks, and simplifying their usage. This paper takes a different approach and proposes a novel execution model to achieve parallel execution of statica… Show more

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Cited by 49 publications
(29 citation statements)
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References 23 publications
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“…The tasks themselves are self-contained and must execute completely before a dependent task can begin. The notion of a task is best represented by a function in a software implementation as functions are frequently re-used tasks [21]. However, functions are not self-contained as they make calls to other 198 functions before returning.…”
Section: B Measurement Methodologymentioning
confidence: 99%
See 1 more Smart Citation
“…The tasks themselves are self-contained and must execute completely before a dependent task can begin. The notion of a task is best represented by a function in a software implementation as functions are frequently re-used tasks [21]. However, functions are not self-contained as they make calls to other 198 functions before returning.…”
Section: B Measurement Methodologymentioning
confidence: 99%
“…Gupta et. al [21] propose models to parallelize statically-sequential programs written in a suitable data flow fashion. However, their parallel executable functions are identified by programmers.…”
Section: Critical Path Analysismentioning
confidence: 99%
“…Subsequent works include tools for exploiting DDM on commodity multicores [19], [20], and the usage of DDM in HPC [4]. Targeting function level parallelism, Gupta and Sohi applied dataflow analysis to generate multithreaded code from imperative programs [8]. In contrast with the previous approaches, we start with a dataflow program and exploit different levels of parallelism including function calls, loop iteration and fused instructions.…”
Section: Related Workmentioning
confidence: 99%
“…In contrast, an adaptation of Instruction-Level Parallelism (ILP) scheduling algorithm to Task-Level Parallelism (TLP) provides a new insight to utilize the MPSoC platform effectively. Current cutting-edge studies such as Task Superscalar [Etsion et al 2010] and Gupta and Sohi [2011] explore new research directions into managing heterogeneous CMPs at a higher abstraction level. However, both approaches address the out-of-order task execution on a dedicated architecture without considerations for FPGA-based MPSoC platforms.…”
Section: Introductionmentioning
confidence: 99%