Platform-independent analysis of function-level communication in workloads

Nilakantan, Siddharth; Hempstead, Mark

doi:10.1109/iiswc.2013.6704685

Cited by 8 publications

(3 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A common method for HW/SW partitioning is to profile the application to find the performance hotspot region. These regions are candidates for FPGA acceleration, as long as the overhead of communication with CPU is not significant [15]. To perform hotspot analysis on big data applications, we use Intel Vtune to select the common hotspot modules of the applications running on big and little cores.…”

Section: Performance Hotspot and Post-acceleration Cpu Code Charactermentioning

confidence: 99%

Heterogeneous chip multiprocessor architectures for big data applications

Homayoun

2016

Proceedings of the ACM International Conference on Computing Frontiers

View full text Add to dashboard Cite

Emerging big data analytics applications require a significant amount of server computational power. The costs of building and running a computing server to process big data and the capacity to which we can scale it are driven in large part by those computational resources. However, big data applications share many characteristics that are fundamentally different from traditional desktop, parallel, and scale-out applications. Big data analytics applications rely heavily on specific deep machine learning and data mining algorithms, and are running a complex and deep software stack with various components (e.g. Hadoop, Spark, MPI, Hbase, Impala, MySQL, Hive, Shark, Apache, and MangoDB) that are bound together with a runtime software system and interact significantly with I/O and OS, exhibiting high computational intensity, memory intensity, I/O intensity and control intensity. Current server designs, based on commodity homogeneous processors, will not be the most efficient in terms of performance/watt for this emerging class of applications. In other domains, heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. A heterogeneous architecture integrates cores with various micro-architectures and accelerators to provide more opportunity for efficient workload mapping. In this work, through methodical investigation of power and performance measurements, and comprehensive system level characterization, we demonstrate that a heterogeneous architecture combining high performance big and low power little cores is required for efficient big data analytics applications processing, and in particular in the presence of accelerators and near real-time performance constraints.

show abstract

Section: Performance Hotspot and Post-acceleration Cpu Code Charactermentioning

confidence: 99%

Heterogeneous chip multiprocessor architectures for big data applications

Homayoun

2016

Proceedings of the ACM International Conference on Computing Frontiers

View full text Add to dashboard Cite

show abstract

“…The capture tool of SynchroTrace is based on the Sigil workload analysis framework [27], which is currently built on top of the Valgrind dynamic binary instrumentation framework, but other instrumentation front-ends are possible. Although Sigil [27] was originally designed to capture communication between functions, for this work it has been adapted to capture local computation of threads and communication between threads. Another important addition of this work is capturing the synchronization behaviors of threads by wrapping prevailing Pthread and OpenMP API calls.…”

Section: Synchrotrace Capture Frameworkmentioning

confidence: 99%

SynchroTrace

Sangaiah

Lui

Jagtap

et al. 2018

ACM Trans. Archit. Code Optim.

Self Cite

View full text Add to dashboard Cite

Trace-driven simulation of chip multiprocessor (CMP) systems offers many advantages over execution-driven simulation, such as reducing simulation time and complexity, allowing portability, and scalability. However, trace-based simulation approaches have difficulty capturing and accurately replaying multithreaded traces due to the inherent nondeterminism in the execution of multithreaded programs. In this work, we present SynchroTrace, a scalable, flexible, and accurate trace-based multithreaded simulation methodology. By recording synchronization events relevant to modern threading libraries (e.g., Pthreads and OpenMP) and dependencies in the traces, independent of the host architecture, the methodology is able to accurately model the nondeterminism of multithreaded programs for different hardware platforms and threading paradigms. Through capturing high-level instruction categories, the SynchroTrace average CPI trace Replay timing model offers fast and accurate simulation of many-core in-order CMPs. We perform two case studies to validate the SynchroTrace simulation flow against the gem5 full-system simulator: (1) a constraint-based design space exploration with traditional CMP benchmarks and (2) a thread-scalability study with HPC-representative

show abstract

“…The binary instrumentation tool is called Sigil [6], a publiclyavailable utility built on top of the Valgrind/Callgrind framework. Through running multi-threaded Splash2 benchmarks, virtual address read and writes are captured, abstracting away any architecture specific behavior.…”

Section: Monte Carlo Exploration Of Thread Mappingmentioning

confidence: 99%

Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping

Salvador

Nilakantan

Taşkın

et al. 2015

2015 28th International Conference on VLSI Design

Self Cite

View full text Add to dashboard Cite

In this paper, we explore the simulation performance trade-off under the lens of Monte Carlo design space exploration for multi-threaded programs and thread mapping. The vehicle used for this exploration will be a recent study, whose novel Google PageRank-based thread mapping approach is compared to hundreds of random mappings, as well as a Round-Robin-based thread mapping approach proposed in this paper used in similar comparisons. The modern simulator landscape presents a choice between cycle-accurate but slow, and fast but inaccurate program simulation. We find that the use of a fast, inaccurate multi-threaded simulator, such as Sniper 5.3, suffers from large nondeterminism in the reported performance of the program. We perform cycle-accurate simulation which demonstrates that the static thread mapping approach does provide benefits in reaching near-optimal design points. Furthermore, the runtime of static thread mapping is significantly reduced using a cycle-accurate simulator compared to the full Monte Carlo exploration of mapping design points.

show abstract

Platform-independent analysis of function-level communication in workloads

Cited by 8 publications

References 26 publications

Heterogeneous chip multiprocessor architectures for big data applications

Heterogeneous chip multiprocessor architectures for big data applications

SynchroTrace

Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping

Contact Info

Product

Resources

About