Dataflow programming model for reconfigurable computing

Gantel, Laurent; Khiar, Amel; Miramond, Benoît; Benkhelifa, Amine; Lemonnier, Fabrice; Kessal, Lounis

doi:10.1109/recosoc.2011.5981505

Cited by 9 publications

(6 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some works focus on specifying and unifying the programming model for hybrid CPU/FPGA systems by using multithreading programming concepts. The BORPH operating system [9], ReconOS [10], the HThread project [14], and the FOSFOR project [15] use such approach. In summary, in these works, a task performed in hardware is seen with the same semantics as a software thread, and a hardware system call interface is provided to hardware components.…”

Section: Related Workmentioning

confidence: 99%

“…Although these works establish a uniform interface for both hardware and software, they still rely on hardware development at RTL level, hindering the effective unification between hardware and software programming models. For instance, in ReconOS [10] and FOSFOR [15], hardware user logic must be explicitly synchronized to match the state machines that control the communication primitives.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A metaprogrammed C++ framework for hardware/software component integration and communication

Mück

Fröhlich

2014

Journal of Systems Architecture

View full text Add to dashboard Cite

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A metaprogrammed C++ framework for hardware/software component integration and communication

Mück

Fröhlich

2014

Journal of Systems Architecture

View full text Add to dashboard Cite

“…The issue of heterogeneity programmability is recurrent in the FPGA domain. In the FOSFOR project [7], a common multi-thread execution model is proposed with the corresponding services whatever the thread is executed on a general purpose processor or in a reconfigurable zone as a dedicated IP [8]. In the project FREIA [9], a common interface has been defined to control any type of accelerators in a master-slave execution model.…”

Section: State Of the Artmentioning

confidence: 99%

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Lemonnier

Millet

Almeida

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

View full text Add to dashboard Cite

Abstract-This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities brought from smart heuristics. Thus, we propose a virtualisation layer which provides a higher abstraction level to mask the underlying heterogeneity present in such architectures. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. The upcoming generation of applications include smart cameras, drones, and cognitive radio. In order to facilitate the architecture adaptation under different scenarios, we propose a programming model that considers both static and dynamic behaviors. This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies. Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.

show abstract

“…Each one of these processing elements is more or less suited to certain types of tasks. We specified and implemented a HRSoC platform in the FOSFOR project [13] (Flexible Operating System FOr Reconfigurable platform). This project aimed to define a reconfigurable multicore heterogeneous platform ( Fig.1).…”

Section: Context and Motivationsmentioning

confidence: 99%

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

Gantel

Benkhelifa

Lemonnier

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

Self Cite

View full text Add to dashboard Cite

Heterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneous processing elements in a single chip. Namely, several processors, hardware accelerators as well as communication networks between all these components. In order to leverage the programming complexity of this kind of platform, applications are described with software threads, running on processors, and hardware threads, running on FPGA partitions. Combining techniques such as dynamic and partial reconfiguration and partial readback with the knowledge of the bitstream structure offer the ability to target several partitions using a unique configuration file. Such a feature permits to save critical memory resources. In this article, we propose to tackle the issue of designing fully independent partitions, and especially to avoid the routing conflicts which can occur when using the standard Xilinx FPGA design flow. To achieve the relocation process successfully, we propose a new design flow dedicated to the module relocation, using the standard tools and based on the Isolation Design Flow (IDF), a special flow provided by Xilinx for secure FPGA applications.

show abstract

Dataflow programming model for reconfigurable computing

Cited by 9 publications

References 13 publications

A metaprogrammed C++ framework for hardware/software component integration and communication

A metaprogrammed C++ framework for hardware/software component integration and communication

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

Contact Info

Product

Resources

About