Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

Gantel, Laurent; Benkhelifa, Mohamed El Amine; Lemonnier, Fabrice; Verdier, François

doi:10.1109/reconfig.2012.6416763

Cited by 15 publications

(7 citation statements)

References 20 publications

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“…This lack of flexibility has induced the development of several academic tools that tried to provide additional reconfiguration capabilities. In the case of Xilinx devices, the first tools appeared for the outdated ISE design environment, and they focused mainly on relocation, such as the works in [22] and [23]. Later on, more comprehensive tools appeared targeting flexible VAs, such as Recobus [19], and more efficient reconfigurable interfaces, such as Go Ahead [18] and Dreams [15].…”

Section: A Coarse Granularitymentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

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Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This paper proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this paper proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

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Section: A Coarse Granularitymentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

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“…Different tools have been proposed in the last years targeting the design of relocatable DPR systems [1][2][3][4][5][6][7][8][9]. The most significant ones are analyzed in this section.…”

Section: State Of the Artmentioning

confidence: 99%

“…Different tools have been proposed over the years in the academia [1][2][3][4][5][6][7] with the aim of extending the capabilities offered by Xilinx commercial tools for the design of reconfigurable systems. Most of these tools worked under the ISE design suite, and they based their operation on the proprietary Xilinx Design Language (XDL) [10].…”

Section: Introductionmentioning

confidence: 99%

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado

Zamacola

Martínez

Mora

et al. 2018

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Dynamic partial reconfiguration is considered a great technique to increase flexibility in FPGA designs. However, partial reconfiguration flows supported by commercial tools, such as Xilinx Vivado, still have many limitations. Foremost among them are the lack of support for relocation, which leads to an increase in the on-system memory requirements and the synthesis time, as well as a reduced flexibility when it comes to the definition of reconfigurable regions. Several academic tools have appeared over the years to improve commercial flows. However, the technology shift from ISE to Vivado has left most of these tools unusable for newer FPGAs, including most of the Xilinx Series-7 devices. In this paper, authors present IMPRESS, a TCL scriptbased tool for the automated generation of relocatable partial bitstreams under Vivado, with a strong focus on the ease of use and the system flexibility. Special support is provided for the implementation of reconfigurable systems that include IP blocks generated with Vivado HLS and standardized bus interfaces. A stream-based reconfigurable architecture for image filtering, implemented in a fully automated manner on a Zynq SoPC, is provided as a use case of the tool.

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“…Related research papers [12], [13] used the Xilinx IDF to design relocatable modules. Those works, however, are not targeting design isolation as needed to implement secure or reliable systems.…”

Section: Related Work a Isolation Design Flowsmentioning

confidence: 99%

IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

Pham¹,

Horta²,

Koch³

et al. 2018

2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC)

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FPGA devices have been used widely in many industrial domains, but only limitedly in secure and safety-critical applications, which have special requirements for the physical implementation, such as module isolation. This is partly due to limited functionality available with current FPGA vendors' tools and flows. To extend FPGA's appearance in secure and safetycritical applications, we propose an alternative flow for isolation design called the Isolated Partial Reconfiguration Design Flow (IPRDF) in this paper. Systems designed by the proposed IPRDF are not only fully isolated but also support partial reconfiguration of insulated modules. This allows building secure and dependable systems that can use partial reconfiguration to mitigate from single-event upsets (SEUs) and that are more tolerant to aging and device imperfections. Further, this also allows information assurance applications to benefit from hardware module isolation and run-time reconfigurability. Case studies on isolated Triple Modular Redundancy (TMR) and single-chip cryptographic (SCC) designs are presented to demonstrate capabilities and advantages of the proposed IPRDF methodology.

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Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

Cited by 15 publications

References 20 publications

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado

IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

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