DC and RF characteristics of depletion-mode GaAs MOSFET employing a thin Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) gate dielectric layer

Planar GaAs(100) depletion-mode (D-mode) metal-oxide-semiconductor field-effect transistors (MOSFETs) as passivated with in-situ deposited Al2O3/Y2O3 dielectric have shown enhancement of the drain current by 167% and 333% as the gate voltage (Vg ) increased from Vg = Vfb = 0.5 V to Vg = 2 V and Vg = 4 V, where Vfb is the flat-band voltage, respectively, much higher than those in the previously published GaAs-based D-mode MOSFETs. In addition, we have achieved a high Ion/Ioff of 107 and a subthreshold slope (SS) of 63 mV/dec, which approaches the thermal limit of 60 mV/dec at 300 K and is the record-low value among planar (In)GaAs MOSFETs. Moreover, using the measured SS data, we have deduced an interfacial trap density (Dit ) of 4.1 × 1011 eV-1cm-2 from our Al2O3/Y2O3/GaAs MOSFET, the lowest among the planar (In)GaAs MOSFETs.

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DC and RF characteristics of depletion-mode GaAs MOSFET employing a thin Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) gate dielectric layer

Cited by 2 publications

References 4 publications

High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon

High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon

GaAs MOSFETs with in situ Y₂O₃ dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation

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DC and RF characteristics of depletion-mode GaAs MOSFET employing a thin Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) gate dielectric layer

Cited by 2 publications

References 4 publications

High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon

High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon

GaAs MOSFETs with in situ Y2O3 dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation

Contact Info

Product

Resources

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GaAs MOSFETs with in situ Y₂O₃ dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation