2006
DOI: 10.1016/j.mseb.2006.08.018
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High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon

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Cited by 78 publications
(42 citation statements)
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“…Recently, we have demonstrated that an in-situ deposited amorphous Si interface passivation layer (IPL) of at least 1.5 nm thickness can be used to reduce interface state density and prevent the Fermi level pinning at GaAs or InGaAs interface with ex-situ high-k oxide [7,8]. It was further shown [9] that the IPL layer thickness can be significantly reduced or it can even be eliminated if the high-k oxide is deposited in-situ without exposure of the III-V surface to environment.…”
Section: Introductionmentioning
confidence: 99%
“…Recently, we have demonstrated that an in-situ deposited amorphous Si interface passivation layer (IPL) of at least 1.5 nm thickness can be used to reduce interface state density and prevent the Fermi level pinning at GaAs or InGaAs interface with ex-situ high-k oxide [7,8]. It was further shown [9] that the IPL layer thickness can be significantly reduced or it can even be eliminated if the high-k oxide is deposited in-situ without exposure of the III-V surface to environment.…”
Section: Introductionmentioning
confidence: 99%
“…In order to sustain a better gate capacitance scalability for metal-oxide-semiconductor (MOS) device application, high-k dielectrics have been deposited onto the III-V semiconductor substrates, such as GaAs and InGaAs [2][3][4][5][6][7][8][9][10][11][12].…”
mentioning
confidence: 99%
“…We note that under the in situ deposition techniques employed here, no As-O-Si bonding is detected in contrast to previous reports. 4 The amount of SiO x that arises as the Si is deposited on the differently prepared surfaces as calculated using Si 2p XPS spectra also differs ͑not shown͒. On an NH 4 OH treated surface exposed to a Si deposition of ϳ1.1 nm, 40% of the Si 2p signal is from some form of SiO x rather than Si-Si bonds.…”
mentioning
confidence: 99%