DC conditions and phase noise of Colpitts oscillator with DGMOST

Videnović-Mišić, Mirjana; Jevtic, M.M.

doi:10.1109/icmel.2004.1314893

Cited by 5 publications

(6 citation statements)

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“…We present in Figure 6(b) a Colpitts oscillator typical case: T = 335.8 ps (period). We use the same values used in [18], except in the component of oscillator Colpitts, we changed the values for obtaining the carrier frequency very near 3 GHz. Mixed mode simulations were carried out using the DESSIS tool in the ISE-TCAD [15].…”

Section: Colpitts Oscillator Build Around the Considered Dgmosmentioning

confidence: 99%

Mixed-Mode Device Modeling of DGMOS RF Oscillators

Bella¹,

Latreche²,

Labiod³

et al. 2014

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A Colpitts oscillator, working around a 3 GHz frequency, contains a double gate Metal Oxide Semiconductor transistor (DGMOS). A mixed-mode analysis is involved, applying a quantum model to the device, whereas the rest of the considered circuit is governed by Kirchhoff's laws. The Linear Time Variant (LTV) model of phase noise is based on the Impulse Sensitivity Function of the Colpitts Oscillator which describes carefully the sensitivity of an oscillator to any impulse current injection in any node of the circuit. Finally, we improve the phase noise modeling, confronting some analytical developments to mixed-mode simulations.

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Section: Colpitts Oscillator Build Around the Considered Dgmosmentioning

confidence: 99%

Mixed-Mode Device Modeling of DGMOS RF Oscillators

Bella¹,

Latreche²,

Labiod³

et al. 2014

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“…It has been shown, in our recent work, that there is high sensitivity of transistor 1/f [7] and oscillator phase [4] noise to the DGMOSFET bias conditions. The purpose of this study is to propose a 1/f DGMOSFET noise model, based on the already known 1/f single MOS transistor noise model [8], as a function of different bias conditions.…”

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confidence: 99%

“…Moreover, 1/f noise increases oscillator phase noise in RF applications [1] and the DC offset level in the baseband part of wireless applications. Therefore, in order to optimize noise performance in upto-date applications, 1/f noise models that describe experimental behaviour well, are required.Dual-gate structures are used in mixers [2], (power) amplifiers [3] and oscillators [4], devices that are building blocks of transceiver front-ends. These devices usually operate in large-signal quasi-periodic conditions where 1/f noise changes in the rhythm of the operating point variation [5] and up-converts into the proximity of the carrier.…”

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Modelling of Dual-Gate MOSFET 1/f Noise in Linear Region

Videnović-Mišić

Jevtic

2007

EUROCON 2007 - The International Conference on "Computer as a Tool"

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This paper presents experimental and numerical results for the dual-gate MOSFET (DGMOSFET) normalized 1/f noise parameter B/I D 2 in linear working region. In modelling, gate-to-gate interelectrode space influence is taken into account with the fitting parameter m, which is defined as the ratio of inner transistors channel lengths. Model and methodology for the normalized 1/f noise parameter calculation for the DGMOSFET linear region have been proposed. The model is based on the ac current approach in the DGMOSFET low-frequency smallsignal noise equivalent circuit and carrier-number fluctuations and correlated mobility fluctuations. It has been shown that discrepancy between measured data and numerical results obtained only by the ΔN model can be explained by use of the gradual channel approximation MOSFET model and the unified 1/f noise model. Keywords-DGMOSFET, flicker noise, device modelling I.INTRODUCTION Continuous scaling of MOSFETs to the sub-micron range has considerably increased the performance of integrated circuits. Some of the results of miniaturisation are higher level of integration in the digital CMOS technology, implementation of the mixed mode (analogue/digital) circuits on the same chip, MOS implementation in analogue RF circuits, applications where a dual-gate MOSFET (DGMOSFET) is of interest. In order to fully understand the potential of new MOSFET circuits with DGMOSFETs in analogue and mixed-mode applications, limitations arising from 1/f noise must be examined. Generally, 1/f noise determines fundamental limits on circuit performance and plays a significant role in analogue circuit design. Moreover, 1/f noise increases oscillator phase noise in RF applications [1] and the DC offset level in the baseband part of wireless applications. Therefore, in order to optimize noise performance in upto-date applications, 1/f noise models that describe experimental behaviour well, are required.Dual-gate structures are used in mixers [2], (power) amplifiers [3] and oscillators [4], devices that are building blocks of transceiver front-ends. These devices usually operate in large-signal quasi-periodic conditions where 1/f noise changes in the rhythm of the operating point variation [5] and up-converts into the proximity of the carrier. As a result, the bandwidth of the transmitted signal is increased, which deteriorates the situation in already scarce frequency resources. As characteristic frequencies of CMOS transistors for RF performance continue to increase [6] and the system-on-chip technology continues to develop, structures such as a DGMOSFET have the potential to replace their heterojunction counterparts [2].

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“…This is particularly the case for devices in transceiver's front-end, such as mixers, oscillators, power amplifiers, frequency multipliers, which usually operate in large-signal quasi-periodic conditions. Therefore, the focus of our recent work has been low-frequency (LF) noise of a DGMOSFET in Colpitts oscillator [6] and phase noise of the same oscillator [7] together with modelling of DGMOSFET 1/f noise under different bias conditions [8]. High sensitivity of the transistor LF and oscillator phase noise to the DGMOSFET working conditions have been noticed.…”

Section: Introductionmentioning

confidence: 99%

Dependence of DGMOSFET 1/f Noise on Transistor Geometry and Technology Parameters

Videnović-Mišić

Jevtic²

2006 25th International Conference on Microelectronics

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In this paper theoretical study of a dual-gate MOSFET (DGMOSFET) 1/f noise and its sensitivity to variation of transistor geometry and technology parameters is presented. Expression for 1/f current noise spectral density S id (f) is obtained using an ac current approach in a DGMOSFET LF small-signal noise equivalent circuit. The results show 1/f S id (f) level increase with L 1 increase and W decrease. For a single MOS transistor and L increase opposite 1/f noise behaviour is observed. In case of a DGMOSFET, not only transistors noise sources influence overall noise but also dynamic transistors parameters and load resistance R L . Sensitivity of S id (f) to source/drain junction depth x j is minimal as a consequence of "long channel" DGMOSFET structure. As for oxide thickness, 1/f noise level show expected increase with t ox increase.

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DC conditions and phase noise of Colpitts oscillator with DGMOST

Cited by 5 publications

References 1 publication

Mixed-Mode Device Modeling of DGMOS RF Oscillators

Mixed-Mode Device Modeling of DGMOS RF Oscillators

Modelling of Dual-Gate MOSFET 1/f Noise in Linear Region

Dependence of DGMOSFET 1/f Noise on Transistor Geometry and Technology Parameters

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