DDR3 SDRAM with a Complete Predictor

Abstract

SUMMARYIn the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.

Implementation of the Complete Predictor for DDR3 SDRAM

“…Namely, the best variant of the zero live time predictor from [1], signed as 2b16, has two bits for every 16 adjacent DRAM rows in the system, used as a saturated counter, with values from 0 to 3. For the adopted 2 GB DDR3 SDRAM structure from [1] with total of 16 banks in the system and 8 k rows per bank, the total number of rows in the system is 128 k. For that number of rows we need 16 kb or 2 kB of SRAM memory. Another important thing considering the implementation are the time intervals needed to execute the two basic operations of the predictors: Lookup and Update.…”

“…Although this predictor seems rather complex, with lots of different hardware elements, the results show that the implementation of the best dead time predictor from [1], signed as sep2, demands only 17,718 equivalent gates. The number of 4-input LUTs used for this predictor is 1,404.…”

“…The Complete Predictor [1] consists of two predictors: a close page predictor and an open page predictor. First the close page predictor predicts whether to close the currently opened DRAM row or to keep it open.…”

“…Since we have already achieved this [1], we wanted to estimate the quantity of hardware needed to implement our predictors. We were mainly interested in seeing what percentage would be spent on SRAM memory and what on all the other hardware elements.…”

“…modern processors (in contemporary processors the DRAM controller is part of the processor). Using the software packet Xilinx ISE WebPack v.8.2, we have implemented the best variants of the zero live time, dead time and open page predictor from [1] on FPGA chip, Xilinx SpartanII family, model xc2v500-6fg256, and we show these results in Sects. 2, 3 and 4, respectively.…”