SUMMARYIn the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

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Performances of DRAM memories are characterized by memory latency and bandwidth. Contemporary DRAM memories more successfully satisfy demands for higher bandwidth than lower latency. In this paper solutions, which may reduce latency of these memories, are investigated. These solutions are two new controller policies called 'Write-miss Only

SUMMARYIn the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.

In modern computing technique, calculation of leading zeros in a data represented as strings of digits is used very often. Those techniques require high speed of the circuit, as well as its fast design. In this paper we propose a design of such a counter, which is applicable to data length of w = 4j bits, for 4 < j ≤ 8 . With this solution it is also possible to process longer data, since the suggested technique offers a good modularity. This is very important, considering the current technology scaling trends. In this paper, a delay behavior of the proposed circuit has also been investigated using equations and VHDL simulation based worst-case delay estimation method. The results show a significant improvement of the circuit speed, compared to the known solutions.