DRAM Controller with a Complete Predictor: Preliminary Results

Stankovic, Vladimir V.; Milenkovic, Nebojsa Z.

doi:10.1109/telsks.2005.1572183

Cited by 8 publications

(8 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It should be said that some of these ideas are already shown in our previous paper [6]. There are 3 main differences between this paper and [6].…”

Section: Basic Ideasmentioning

confidence: 62%

“…There are 3 main differences between this paper and [6]. First, in [6] there are no zero-live-time predictors.…”

Section: Basic Ideasmentioning

confidence: 91%

“…There are 3 main differences between this paper and [6]. First, in [6] there are no zero-live-time predictors. Second, only latencies for the Open Page strategy and the complete predictor are shown in [6].…”

Section: Basic Ideasmentioning

confidence: 91%

See 2 more Smart Citations

DRAM Controller with a Complate Predictor

Stankovic

Milenkovic

2009

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYIn the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

show abstract

“…It should be said that some of these ideas are already shown in our previous paper [6]. There are 3 main differences between this paper and [6].…”

Section: Basic Ideasmentioning

confidence: 62%

“…There are 3 main differences between this paper and [6]. First, in [6] there are no zero-live-time predictors.…”

Section: Basic Ideasmentioning

confidence: 91%

See 1 more Smart Citation

DRAM Controller with a Complate Predictor

Stankovic

Milenkovic

2009

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…For example in [20] and [13] a predictor was used to reduce average DRAM access latency by forecasting whether an open DRAM row should be closed. Both predictors can therefore only forecast a binary result, whether an action should take place or not.…”

Section: Related Workmentioning

confidence: 99%

A generic implementation of a quantified predictor on FPGAs

Thomas

Elhossini

Juurlink

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

Predictors are used in many fields of computer architectures to enhance performance. With good estimations of future system behavior, policies can be developed to improve system performance or reduce power consumption. These policies become more effective if the predictors are implemented in hardware and can provide quantified forecasts and not only binary ones.In this paper, we present and evaluate a generic predictor implemented in VHDL running on an FPGA which produces quantified forecasts. Moreover, a complete scalability analysis is presented which shows that our implementation has a maximum device utilization of less than 5%. Furthermore, we analyze the power consumption of the predictor running on an FPGA. Additionally, we show that this implementation can be clocked by over 210 MHz. Finally, we evaluate a power-saving policy based on our hardware predictor. Based on predicted idle periods, this power-saving policy uses power-saving modes and is able to reduce memory power consumption by 14.3%.

show abstract

“…In [19], [23], a predictor was employed to reduce precharges and activates and thereby reducing the average DRAM access latency. This forecast is used to determine whether an open DRAM row should be closed or kept open and which row to open next to minimize the average access latency.…”

Section: Related Workmentioning

confidence: 99%

A Predictor-Based Power-Saving Policy for DRAM Memories

Thomas

Chandrasekar

Åkesson

et al. 2012

2012 15th Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

Abstract-Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings.In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%.

show abstract

DRAM Controller with a Complete Predictor: Preliminary Results

Cited by 8 publications

References 2 publications

DRAM Controller with a Complate Predictor

DRAM Controller with a Complate Predictor

A generic implementation of a quantified predictor on FPGAs

A Predictor-Based Power-Saving Policy for DRAM Memories

Contact Info

Product

Resources

About