DRAM Controller with a Complate Predictor

Abstract

SUMMARYIn the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

DDR3 SDRAM with a Complete Predictor

“…We have integrated this simulator with a DDR3 SDRAM simulator, written by ourselves. Characteristics of the simulated system are basically the same as in [1]. The main difference is the increased processor clock frequency, which is 3.2 GHz.…”

“…The main difference is the increased processor clock frequency, which is 3.2 GHz. Also, in [1] we have used four cache configurations. Since the simulation results did not show much difference between these various configurations, in this paper we use only one cache configuration -the 'middle' one from [1].…”

“…We have simulated executions of 11 benchmark programs: the 6 SPEC95 programs from [1] (cc1, compress, ijpeg, li, m88ksim, perl), go from SPEC95, bzip2, gcc, mcf from SPEC2000, and anagram. The last one finds all the possible words obtained by combinations of the letters of 3 names: Todd Austin, Scott Breach and Guri Sohi.…”

“…In our previous paper [1], we proposed a DDR SDRAM controller with similar predictors that both close the opened DRAM row and predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on DDR3 SDRAM memories.…”

“…The main advances of this paper compared to [1], besides trying our predictors on DDR3 SDRAM, are: 1. We try a modification of the zero live time predictor and gain the same performance improvements with 16 times less hardware.…”