Access latency reduction in contemporary dram memories

Stankovic, Vladimir V.; Milenkovic, Nebojsa Z.

doi:10.2298/fuee0401081s

Cited by 6 publications

(8 citation statements)

References 7 publications

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“…Figure 3 illustrates one rank interleaving address mapping. Several Studies have examined more involved address mappings with the objective of reducing SDRAM row conflicts [3,16,18,19]. Wei-fen Lin [18] pointed out that address mappings affect performance significantly and proposed an address mapping scheme that XORs the device and bank index with the lower bits of the row address.…”

Section: Related Workmentioning

confidence: 99%

The bit-reversal SDRAM address mapping

Shao

Davis

2005

Proceedings of the 2005 Workshop on Software and Compilers for Embedded Systems - SCOPES '05

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The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access stream increases SDRAM row hit rate, it also increases row conflicts. Mapping of the physical address bits into SDRAM column, row, bank and rank index impacts system performance significantly. A novel address mapping scheme, called bitreversal, is described and experimentally compared against known methods. The bit-reversal address mapping increases SDRAM row hit rate from 43% to 66% by distributing conflicting memory accesses over independent SDRAM banks. Bit-reversal address mapping reduces the average memory access latency by 26% 29% over other methods, resulting in a 11.7%-13.5% reduction of total execution time. The configuration space of bit-reversal address mapping is explored. Finally, limited studies examining the impact of address mapping techniques in conjunction with SDRAM controller policy and virtual paging illustrate that mapping is better suited to virtual memory free embedded systems than desktop workstations incorporating paging mechanisms.

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Section: Related Workmentioning

confidence: 99%

The bit-reversal SDRAM address mapping

Shao

Davis

2005

Proceedings of the 2005 Workshop on Software and Compilers for Embedded Systems - SCOPES '05

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“…When using the second policy, a row is being closed after every access, so the latency is always the samethe sum Tra+Tca. The Open Row Policy gives good results if there is a good memory access locality, and [5], [6] we have already considered various possibilities of obtaining hybrid policies, which use the advantages of both policies. The goal is to achieve a policy more efficient than the both basic policies, and in that way, to decrease the DRAM latency.…”

Section: Basic Ideamentioning

confidence: 99%

“…This is the basis of papers in which address remappings are considered, which transform memory addresses into banks, rows and columns that optimize DRAM performances for certain memory access patterns [4], [5].…”

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confidence: 99%

DRAM Controller with a Close-Page Predictor

Stankovic

Milenkovic

2005

EUROCON 2005 - The International Conference on "Computer as a Tool"

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Better insight of programs behavior can help in overcoming large speed difference of central processors and main memories implemented with DRAM chips. It allows us to predict required next actions, based on observed main memory access patterns, which can hide some time components in accessing DRAM memory. Authors of this paper proposed in [1] a simple dead time predictor which helps in predicting when to close the opened DRAM row. In this paper this predictor is further improved by adding a zero live time predictor. The zero live time predictor, by its essence, completes the dead time predictor from [1].

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“…This makes that we can influence DRAM memory performances (latency) by controlling the data placement into banks and rows. This is the basis of papers in which address remappings are considered, which transform memory addresses into banks, rows and columns that optimize DRAM performances for certain memory access patterns [3], [4].…”

Section: Introductionmentioning

confidence: 99%

“…Open Row Policy gives good results if there is a good memory access locality, and Close Row Autoprecharge Policy gives good results if DRAM accesses have mostly random character. In some of our previous papers [4], [5] we have already considered various possibilities for obtaining hybrid policies, which use the advantages of both policies. The goal is to achieve a policy more efficient than both the Open Row and Close Row Autoprecharge Policy, and in that way, to decrease the DRAM latency.…”

Section: Introductionmentioning

confidence: 99%

DRAM Controller with a Complate Predictor

Stankovic

Milenkovic

2009

IEICE Trans. Inf. & Syst.

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SUMMARYIn the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

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Access latency reduction in contemporary dram memories

Cited by 6 publications

References 7 publications

The bit-reversal SDRAM address mapping

The bit-reversal SDRAM address mapping

DRAM Controller with a Close-Page Predictor

DRAM Controller with a Complate Predictor

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