DDT: A Research Tool for Automatic Data Distribution in High Performance Fortran

Ayguadé, Eduard; García, Jordi; Gironès, Mercè; Grande, M. Luz; Labarta, Jesús

doi:10.1155/1997/780152

Cited by 8 publications

(6 citation statements)

References 11 publications

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“…With the constant development of NoC technology, the NoC technology will be used in various fields, and the mapping [13][14][15] question of the NoC platform is a very important part in the design process of NoC for the application of different direction for working out the most good mapping, which will effectively reduce the power consumption and the cost of NoC. The on-chip network mapping is IP correspond to the blocks of the topology to meet certain restrictions, such as bandwidth limitations.…”

Section: Description Of the Problemmentioning

confidence: 99%

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Energy Consumption Oriented Network-on-Chip Mapping Method

Wang¹

2013

JNW

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In this paper, mapping algorithm has been mainly studied. The main work and contribution have been generalized as follows: Through the research of existing onchip network mapping algorithm and global optimization algorithm, a multi-step mapping algorithm for low-power consumption have been designed, which is combined with the task allocation and the task scheduling. Compared with the traditional mapping algorithm, the algorithm in this paper takes the factors of task scheduling and allocation into account, mapping algorithm has three steps: task scheduling, IP core mapping and data block mapping. The simulation results show that the mapping method in this paper can effectively reduce Network-on-Chip (NoC) power consumption. Index Terms-Mapping Algorithm; Task Scheduling; IP Core Mapping; Data Block Mapping; Network-on-Chip (NoC) I. INTRODUCTION With the improvement of SoC (System-on-Chip), NoC is an intercommunication-based network system implemented on an integrated circuit. As the development of IC technology, SoC based on the traditional bus architecture has been unable to meet the increasing requirement of network communication. As an important technology of NoC, it plays an important role in the performance of the network, such as throughput, delay, fault tolerance and load balance. At present, many research institutions and companies engaged in on-chip network research in which the better-known institutions have Satanford University [1], Princeton University [2], the University of Bologna, KTH [3], the SGS-Thomson semiconductor company, Arteriscompany France Curie University [4], the Royal Swedish Institute of Technology, the Netherlands PHILIP laboratories. Networks on chip has arisen as a solution to the poor wire scaling and increasing complexity of large System on Chip (SoC) design. NoCs aim to replace long shared bus wires with scalable switched networks with higher performance, predictable wiring and better interconnect properties. These networks can be made latency insensitive, simplifying the design of complex systems since communication and computation problems can be treated separately. Although NoCs provide many benefits, they add additional logic complexity to the communication architecture. Power consumption in the communication architecture is a major bottleneck in current design [7] and hence, energy-aware optimizations for NoCs are of primary importance. Several optimization methods have been proposed to reduce energy consumption through application specific customizations. These include: customized router buffer sizing [6]; custom topology generation [12]; adaptive routing [16]; and mapping processing elements to tiles [17]. The applications of NoC can be static or dynamic. Regular topologies such as mesh and torus are often used to overcome such plug-and-play compatibility issues. It has become evident through research that the application specific NoC architecture is superior to regular topologies in terms of power consumption and NoC resources [5]. Regular topologies tend to assume that ...

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Section: Description Of the Problemmentioning

confidence: 99%

“…The third stage is the data unit mapping [22], and the mapping task called data units are mapped to the physical memory of IP core unit in this stage, and the cost function of the mapping is as follows:…”

Section: Data Unit Mappingmentioning

confidence: 99%

Energy Consumption Oriented Network-on-Chip Mapping Method

Wang¹

2013

JNW

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“…In this section, we summarize a few selected papers. In addition to Li and Chen's alignment method 13, 1 4 ] (already described in Section 2.1), we describe three papers by T andri and Abdelrahman 17], Kelly and Pugh 9], and Ayguad e et al 4,3 ], whose goal is similar to ours. Next we present results by Gupta and Banerjee 7] and Li and Chen 12] on identifying structured communications and estimating their weight.…”

Section: Related Workmentioning

confidence: 99%

“…Ayguad e et alAyguad e et al4,3] consider programs constituted of several consecutive perfect loop nests L 1 L 2 L n . All arrays are assumed to have the same dimension d. They describe their method for 1D-and 2D-grids, but we only deal with 1D-grids in this short survey.…”

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confidence: 99%

Alignment and Distribution Is Not (Always) NP-Hard

Boudet¹,

Rastello²,

Robert³

2001

Journal of Parallel and Distributed Computing

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In this paper, an efficient algorithm to simultaneously implement array alignment and dataÂcomputation distribution is introduced and evaluated. We revisit previous work of J. Li and M. Chen (in``Frontiers 90: The Third Symposium on the Frontiers of Massively Parallel Computation,'' pp. 424 433, College Park MD, Oct. 1990; and J. Parallel Distrib. Comput. 13 (1991), 213 221), and we show that their alignment step should not be conducted without preserving the potential parallelism. In other words, the optimal alignment may well sequentialize computations, whatever the distribution afterward. We provide an efficient algorithm that handles alignment and dataÂcomputation distribution simultaneously. The good news is that several important instances of the whole alignment Âdistribution problem have polynomial complexity, while alignment itself is NP-complete (Li and Chen, 1990). Academic Press

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“…based parallel execution platforms (e.g., an NoC based chip multiprocessor, CMP) in an energy-aware fashion. While one may try to employ known code parallelization techniques from the high-performance computing domain [2,3,10,24], such techniques are not very suitable for NoC-based CMPs mainly because (1) these techniques are mostly performance oriented and do not consider other important metrics such as power and (2) they do not take the network structure explicitly into account, and thus, the only distinction (as far as the locations of data elements are concerned) these prior techniques consider is local versus nonlocal data. In an NoC based execution environment, however, the exact location of non-local data matters a lot, in particular from the power consumption angle.…”

Section: Introductionmentioning

confidence: 99%

Application mapping for chip multiprocessors

Chen

Li²,

Son

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing. In the first step, the application code is parallelized and the resulting parallel threads are assigned to virtual processors. The second step implements a virtual processor-to-physical processor mapping. The goal of this mapping is to ensure that the threads that are expected to communicate frequently with each other are assigned to neighboring processors as much as possible. In the third step, data elements are mapped to memories attached to CMP nodes. The main objective of this mapping is to place a given data item into a node which is close to the nodes that access it. The last step of our approach determines the paths (between memories and processors) for data to travel in an energy efficient manner. In this paper, we describe the compiler algorithms we implemented in detail and present an experimental evaluation of the framework. In our evaluation, we test our entire framework as well as the impact of omitting some of its steps. This experimental analysis clearly shows that the proposed framework reduces energy consumption of our applications significantly (27.41% on average over a pure performance oriented application mapping strategy) as a result of improved locality of data accesses.

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DDT: A Research Tool for Automatic Data Distribution in High Performance Fortran

Cited by 8 publications

References 11 publications

Energy Consumption Oriented Network-on-Chip Mapping Method

Energy Consumption Oriented Network-on-Chip Mapping Method

Alignment and Distribution Is Not (Always) NP-Hard

Application mapping for chip multiprocessors

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