2016
DOI: 10.6113/jpe.2016.16.2.425
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Dead-Time for Zero-Voltage-Switching in Battery Chargers with the Phase-Shifted Full-Bridge Topology: Comprehensive Theoretical Analysis and Experimental Verification

Abstract: This paper presents a comprehensive theoretical analysis and an accurate calculation method of the dead-time required to achieve zero-voltage-switching (ZVS) in a battery charger with the phase-shifted full-bridge (PSFB) topology. Compared to previous studies, this is the first time that the effects of nonlinear output filter inductance, varied Miller Plateau length, and blocking capacitors have been considered. It has been found that the output filter inductance and the Miller Plateau have a significant influ… Show more

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Cited by 6 publications
(3 citation statements)
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“…In the half-bridge converter, asymmetric control is required to use the zero-voltage switching (ZVS) method, and causes unbalanced voltage and current stress of the switches. Contrary to other insulated converters, in the full-bridge converter, the ZVS method can be used without asymmetric control thus its control method can be simplified [11]. Therefore, in general, the full-bridge converter is used for the LDC.…”
Section: Introductionmentioning
confidence: 99%
“…In the half-bridge converter, asymmetric control is required to use the zero-voltage switching (ZVS) method, and causes unbalanced voltage and current stress of the switches. Contrary to other insulated converters, in the full-bridge converter, the ZVS method can be used without asymmetric control thus its control method can be simplified [11]. Therefore, in general, the full-bridge converter is used for the LDC.…”
Section: Introductionmentioning
confidence: 99%
“…Descriptions of state equation are given because the characteristics of MOSFET in the process of turning-on and turning-off are combined. In [16], the influence of load current on miller platform of MOSFET is considered in the equivalent model. Furthermore, the dead time of two bridges can be effectively adjusted.…”
Section: Introductionmentioning
confidence: 99%
“…Besides, the higher I minZV S , the higher turn-off losses, although E OF F are much lower than E ON in WBG semiconductors (Table 2.3), and also more CM EMI is generated [68]. However, it can be noticed that to set the most optimal I minZV S , t DB should change for any d to exactly match Once I minZV S is calculated, the time needed to charge/discharge the parasitic capacitance can be deduced by analyzing the equivalent circuit [136]. Referring to the transition depicted in Figure 4.30, which corresponds to the angle α 1 while T 14 is on (see Figure 4.27(b)), the left full-bridge current path just after turn-off can be depicted as in Figure 4.…”
Section: Determination Of Minimum I Minzv S By Parasitic Capacitancementioning
confidence: 99%