Deadlock-free connection-based adaptive routing with dynamic virtual circuits

Turner, Yoshio; Tamir, Yuval

doi:10.1016/j.jpdc.2006.08.012

Cited by 5 publications

(3 citation statements)

References 34 publications

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“…Virtual circuit routing is a connection oriented communication service that emulates circuit switching. In virtual circuit routing, the packets are delivered by means of packet switching where the connection is established before any packets are transferred and handshaking overhead produce during the connection establishment phase [21]. However, the bit rate and latency service are similar to circuit switching which might be different in a virtual circuit routing due to three main differences.…”

Section: Virtual Circuit Routingmentioning

confidence: 99%

Power and chip-area aware network-on-chip simulation

Gharan¹

2021

Preprint

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Among different communication architectures employed in Multi-Processor Systems-on-Chip (MPSoC), Network-on-Chip (NoC) is recognized as a state of the art paradigm that can overcome on-chip communication challenges. In this thesis, we introduce the simulation of NoC systems. The structure of a new SystemC based NoC simulator (FANOOS) is presented in this thesis. We discuss various components of the simulator by presenting their SystemC code. We also provide an analytical methodology that employs the micro-architectural level of NoC routers and links by considering their power and chip are requirements. An evaluation flow for early stage design of NoC is introduced.

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Section: Virtual Circuit Routingmentioning

confidence: 99%

Power and chip-area aware network-on-chip simulation

Gharan¹

2021

Preprint

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“…Time division circuit-switching flow-control has also been proposed [14]. Connection-based routing can also be used for deadlock-free adaptive routing [20] by allowing intermediate nodes to tear down and modify end-to-end virtual circuits. A hybrid packet-connected circuit has also been proposed, requiring the routers to have buffer space only for request packets [21].…”

Section: Related Workmentioning

confidence: 99%

Elastic Buffer Flow Control for On-Chip Networks

Dally

2013

IEEE Trans. Comput.

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This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel buffers (VCBs). With this approach, the channels themselves act as distributed FIFO buffers. Without VCBs, and hence virtual channels (VCs), deadlock prevention is achieved by duplicating physical channels. We develop a channel occupancy detector to apply universal globally adaptive load-balancing (UGAL) routing to load balance traffic in networks using EBs. Using EBs results in up to 8% (12% for low-swing channels) improvement in peak throughput per unit power compared to a VC flow-control network. These gains allow for a wider network datapath to be used to offset the removal of VCBs and increase throughput for a fixed power budget. EB networks have identical zero-load latency to VC networks operating under the same frequency. The microarchitecture of an EB router is considerably simpler than a VC router because allocators and credits are not required. For 5×5 mesh routers, this results in an 18% improvement in the cycle time.

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“…Flexibility and in-order delivery can be achieved using a virtual circuit (VC) mechanism [21,22]. The resources, which can include link capacity, buffers, routing entries etc., are reserved during VC setup, before the first packet of the connection is sent, and all data packets follow the same path.…”

Section: Adaptive Routingmentioning

confidence: 99%

Improving communication-phase completion times in HPC clusters through congestion mitigation

Birk

Zdornov

2009

Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference

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Congestion arises in cluster-based supercomputers due to contention for links, spreads due to oversubscription of communication resources, and reduces performance. We mitigate it using efficient, scalable adaptive routing and explicit rate calculation. We use virtual circuits for in-order packet delivery; path setup is performed by switches locally with no blocking or backtracking. For random permutations in a slightly enriched fat-tree topology, maximum contention is reduced by up to 50% relative to static routing, but only rate control can translate this into actual gain. Unfortunately, TCP's window-based rate control fails because of the low bandwidth-delay product, and small buffers moreover cause congestion spreading even with a single-packet window. InfiniBand's CCA employs multiple parameters, which must apparently be tuned per topology and traffic pattern. Focusing on phase-based applications, we present a distributed explicit rate-assignment algorithm for completion-time minimization of the communication phase (min-max flow completion). Also, a generally applicable packet-injection scheme for a source with different-rate flows that realizes desired rates even with very small switch buffers. Simulations show that adaptive routing alone is ineffective, rate control's effectiveness is limited, yet together they shorten the communication phase by tens of percents. Finally, our explicit rate-calculation algorithm is faster than current reactive schemes.

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Deadlock-free connection-based adaptive routing with dynamic virtual circuits

Cited by 5 publications

References 34 publications

Power and chip-area aware network-on-chip simulation

Power and chip-area aware network-on-chip simulation

Elastic Buffer Flow Control for On-Chip Networks

Improving communication-phase completion times in HPC clusters through congestion mitigation

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