Debug support for complex systems on-chip: a review

Exploring ICMetrics to detect abnormal program behaviour on embedded devices

“…Hence, the proposed work is particularly suitable for providing possible security solutions to commercial off-the-shelf (COTS) products, where the products have many restrictions on modifying their internal programs or hardware architectures. The proposed system can be run on a non-intrusive debug facility, a non-intrusive infrastructure that is generally used during device software development at present in all production devices, that connects to the targeted embedded device through a debug interface [28,29], which means that the proposed system would not affect the performance of the monitored embedded system in terms of additional memory and processor usage. In one of the authors' previous works [30], an implementation of the conventional SOM on a Xilinx Virtex-4 with 40 neurons required only 22.1% of the available 5,184 Kb Block RAM.…”

A Multi-Core Debug Platform for NoC-Based Systems

“…At the same time, because of the high design complexity and the inaccurate abstracted models used in various design phases, existing verification techniques, such as simulation, formal verification, static timing analysis, and emulation cannot guarantee the correctness of the first silicon [11,18]. Since time-to-market dictates the success of a chip, a silicon debug strategy that helps identifying bugs effectively and efficiently is of crucial importance.…”

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

“…Scan chains are widely utilized to support manufacturing test as a design-for-testability feature. Scanbased debug techniques [9], [18], [19] significantly enhance the internal signal observability, however, the system needs to be halted to read out responses from the circuit-under-debug. A trace buffer is an on-chip memory that can store the continuous internal signal information for a limited time period.…”

“…Unlike during pre-silicon verification, the accessibility and visibility of internal signals are very limited in post-silicon debug and hence this is the major challenge in the validation and debug of first silicon. Hence, identifying and resolving problems in ICs after first silicon is a very time consuming and extremely complex task [6], [8], [9], [12]- [14], [17], [20], [22], [23].…”